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TNETV2685FIBZUT7 数据表(PDF) 27 Page - Texas Instruments

部件名 TNETV2685FIBZUT7
功能描述  Digital Media Processor
PDF  191 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

TNETV2685FIBZUT7 数据表(HTML) 27 Page - Texas Instruments

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TMS320DM647
TMS320DM648
www.ti.com
SPRS372H – MAY 2007 – REVISED APRIL 2012
Table 2-4. Terminal Functions (continued)
TERMINAL NAME
NO
TYPE(
INTERNAL
OPER
DESCRIPTION
1)
PULLUP/
VOLT
PULLDOWN
VP2D13/VRXD1
V3
I/O/Z
IPD
3.3 V
Video Port 2 Data 13 or VLYNQ receive data pin [1] (I)
VP2D14/VRXD2
V4
I/O/Z
IPD
3.3 V
Video Port 2 Data 14 or VLYNQ receive data pin [2] (I)
VP2D15/VRXD3
U1
I/O/Z
IPD
3.3 V
Video Port 2 Data 15 or VLYNQ receive data pin [3] (I)
VP2D16/VTXD0
U3
I/O/Z
IPD
3.3 V
Video Port 2 Data 16 or VLYNQ transmit data pin [0] (O)
VP2D17/VTXD1
U2
I/O/Z
IPD
3.3 V
Video Port 2 Data 17 or VLYNQ transmit data pin [1] (O)
VP2D18/VTXD2
U5
I/O/Z
IPD
3.3 V
Video Port 2 Data 18 or VLYNQ transmit data pin [2] (O)
VP2D19/VTXD3
U4
I/O/Z
IPD
3.3 V
Video Port 2 Data 19 or VLYNQ transmit data pin [3] (O)
VIDEO PORT 3 OR EMIFA
VP3CLK0/ AECLKIN
T1
I
IPD
3.3 V
Video Port 3 Clock 0 (I) or EMIFA external input clock (I)
VP3CLK1/
P1
I/O/Z
IPD
3.3 V
Video Port 3 Clock 1 or EMIFA output clock (O/Z)
AECLKOUT
VP3CTL0/
T2
I/O/Z
IPU
3.3 V
Video Port 3 Control 0 or Asynchronous memory write
AAWE/ASWE
enable/Programmable synchronous interface write-enable
VP3CTL1/ AR/W
R1
I/O/Z
IPU
3.3 V
Video Port 3 Control 1 or Asynchronous memory read/write (O/Z)
VP3CTL2/
P2
I/O/Z
IPU
3.3 V
Video Port 3 Control 2 or Asynchronous/Programmable
AAOE/ASOE
synchronous memory output-enable (O/Z)
VP3D02/AED00
T6
I/O/Z
IPU
3.3 V
Video Port 3 Data 2 or EMIFA External Data 0
VP3D03/AED01
T5
I/O/Z
IPU
3.3 V
Video Port 3 Data 3 or EMIFA External Data 1
VP3D04/AED02
T4
I/O/Z
IPU
3.3 V
Video Port 3 Data 4 or EMIFA External Data 2
VP3D05/AED03
T3
I/O/Z
IPU
3.3 V
Video Port 3 Data 5 or EMIFA External Data 3
VP3D06/AED04
R6
I/O/Z
IPU
3.3 V
Video Port 3 Data 6 or EMIFA External Data 4
VP3D07/AED05
R5
I/O/Z
IPU
3.3 V
Video Port 3 Data 7 or EMIFA External Data 5
VP3D08/AED06
R4
I/O/Z
IPU
3.3 V
Video Port 3 Data 8 or EMIFA External Data 6
VP3D09/AED07
R3
I/O/Z
IPU
3.3 V
Video Port 3 Data 9 or EMIFA External Data 7
VP3D12/AED08
R2
I/O/Z
IPU
3.3 V
Video Port 3 Data 12 or EMIFA External Data 8
VP3D13/AED09
P6
I/O/Z
IPU
3.3 V
Video Port 3 Data 13 or EMIFA External Data 9
VP3D14/AED10
P5
I/O/Z
IPU
3.3 V
Video Port 3 Data 14 or EMIFA External Data 10
VP3D15/AED11
P4
I/O/Z
IPU
3.3 V
Video Port 3 Data 15 or EMIFA External Data 11
VP3D16/AED12
P3
I/O/Z
IPU
3.3 V
Video Port 3 Data 16 or EMIFA External Data 12
VP3D17/AED13
N4
I/O/Z
IPU
3.3 V
Video Port 3 Data 17 or EMIFA External Data 13
VP3D18/AED14
N6
I/O/Z
IPU
3.3 V
Video Port 3 Data 18 or EMIFA External Data 14
VP3D19/AED15
N5
I/O/Z
IPU
3.3 V
Video Port 3 Data 19 or EMIFA External Data 15
VIDEO PORT 4 OR EMIFA
VP4CLK0/AARDY
L1
I
IPU
3.3 V
Video Port 4 Clock 0 (I) or Asynchronous memory ready input (I)
VP4CLK1
K1
I/O/Z
IPD
3.3 V
Video Port 4 Clock 1
VP4CTL0/ABA0
J2
I/O/Z
IPD
3.3 V
Video Port 4 Control 0 or EMIFA bank address control (ABA[1:0])
(O/Z). Active-low bank selects for the 16-bit EMIFA. When
interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of
the byte address. For an 8-bit asynchronous interface, ABA[1:0]
are used to carry bits 1 and 0 of the byte address.
VP4CTL1/ABA1
J1
I/O/Z
IPD
3.3 V
Video Port 4 Control 1 or EMIFA bank address control (ABA[1:0])
(O/Z). Active-low bank selects for the 16-bit EMIFA. WHEN
interfacing to 16-bit asynchronous devices, ABA1 carries bit 1 of
the byte address. For an 8-bit asynchronous interface, ABA[1:0]
are used to carry bits 1 and 0 of the byte address.
Copyright © 2007–2012, Texas Instruments Incorporated
Device Overview
27
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Product Folder Link(s): TMS320DM647 TMS320DM648



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