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TNETV2685FIBZUT7 数据表(PDF) 96 Page - Texas Instruments |
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TNETV2685FIBZUT7 数据表(HTML) 96 Page - Texas Instruments |
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96 / 191 page  TMS320DM647 TMS320DM648 SPRS372H – MAY 2007 – REVISED APRIL 2012 www.ti.com 6.8 Interrupts The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for each of the 12 CPU interrupts is user programmable. Also, the interrupt controller controls the generation of the CPU exception, NMI, and emulation interrupts and the generation of AEG events. Table 6-27 summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP interrupt control, see TMS320DM647/TMS320DM648 DSP Subsystem Reference Guide (literature number SPRUEU6). Table 6-26. DSP Interrupt Events DSP EVENT INTERRUPT SOURCE INTERRUPT EVENT NUMBER 0 EVT0 Output of event combiner 0, for events 1 – 31 1 EVT1 Output of event combiner 1, for events 32 – 63 2 EVT2 Output of event combiner 2, for events 64 – 95 3 EVT33 Output of event combiner 3, for events 96 – 127 4-8 Reserved 9 EMU_DTDMA ECM interrupt for: • Host scan access event • DTDMA transfer complete event • AET interrupt event 10 Reserved Reserved 11 EMU_RTDXRX RTDX receive complete event 12 EMU_RTDXTX RTDX transmit complete event 13 IDMA0 EMC C64x+ EMC 0 event 14 IDMA1 EMC C64x+ EMC 1 event 15 DSPINT Host (PCI/HPI) to DSP interrupt event 16 I2CINT I2C interrupt event 17 Reserved Reserved 18 AEASYNCERR event EMIFA Error Interrupt event 19 TINT2L Timer interrupt low event 20 TINT2H Timer interrupt high event 21 TINT3L Timer interrupt low event 22 TINT3H Timer interrupt high event 23 PSCINT PSC-ALLINT event 24 TPCC_GINT EDMA3 channel global completion interrupt event 25 SPIINT0 SPI Interrupt 26 SPIINT1 SPI Interrupt 27 DSQINT VICP – Sqr (DSP int) 28 IMXINT VICP – IMX 29 VLCDINT VICP - VLCD 30 -31 Reserved Reserved 32 RX_PULSE Ethernet Subsystem RX pulse interrupt event 33 RX_THRESH_PULSE Ethernet Subsystem RX threshold interrupt event 34 TX_PULSE Ethernet Subsystem TX pulse interrupt event 35 MISC_PULSE Ethernet Subsystem MISC pulse interrupt event 36 UART_INT UART Interrupt 37 VP0_INT VP0 Interrupt 38 VP1_INT VP1 Interrupt 39 VP2_INT VP2 Interrupt 40 VP3_INT VP3 Interrupt 96 Peripheral Information and Electrical Specifications Copyright © 2007–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM647 TMS320DM648 |
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