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LNBH25LS 数据表(PDF) 10 Page - STMicroelectronics |
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LNBH25LS 数据表(HTML) 10 Page - STMicroelectronics |
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10 / 30 page ![]() Application information LNBH25LS 10/30 DocID026753 Rev 3 circuit current protection either statically (simple current clamp) or dynamically by the PCL bit of the I²C data 3 register. When the PCL (pulsed current limiting) bit LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for TON time 90 ms, after which the output is set in shutdown for TOFF time of typically 900 ms. Simultaneously, the diagnostic OLF I²C bit of the system register is set to “1”. After this time has elapsed, the output is resumed for a time TON. At the end of TON, if the overload is still detected, the protection circuit cycles again through TOFF and TON. At the end of a full TON in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW after a register reading is done. Typical TON +TOFF time is 990 ms and an internal timer determines it. This dynamic operation can greatly reduce the power dissipation in short-circuit condition, still ensuring excellent power-on startup in most conditions. However, there could be some cases in which a highly capacitive load on the output may cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=1) and, then, switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” when the current clamp limit is reached and returns LOW when the overload condition is cleared and register reading is done. After the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the data 4 register. If OLR=1, all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. To re- enable output stage, the VSEL bits must be set again by the microprocessor, and the OLF bit is reset to “0” after a register reading operation. If OLR=0, output is automatically re-enabled as soon as the overload condition is removed, and the OLF bit is reset to “0” after a register reading operation. 2.12 OTF: thermal protection and diagnostic The LNBH25LS is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and the linear regulator are shut off, the diagnostic OTF bit in the status1 register is set to “1”. After the overtemperature condition is removed, normal operation can be resumed in two ways, according to the THERM I²C bit on the data 4 register. If THERM=1, all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. To re-enable output stage, the VSEL bits must be set again by the microprocessor, while the OTF bit is reset to “0” after a register reading operation. If THERM=0, output is automatically re-enabled as soon as the overtemperature condition is removed, while the OTF bit is re set to “0” after a register reading operation. |
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