LNBH25LS

List of figures

DocID026753 Rev 3

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List of figures

Figure 1: Block diagram ..............................................................................................................................6

Figure 2: Tone enable and disable timing (using external waveform) ........................................................7

Figure 3: Tone enable and disable timing (using envelope signal) ............................................................8

Figure 4: Surge protection circuit ................................................................................................................9

Figure 5: Pin connections (top view).........................................................................................................11

Figure 6: DiSEqC 1.x application circuit ...................................................................................................14

Figure 7: Data validity on the I²C bus .......................................................................................................17

Figure 8: Timing diagram of I²C bus .........................................................................................................17

Figure 9: Acknowledge on the I²C bus......................................................................................................17

Figure 10: Example of writing procedure starting with first data address 0X2 .........................................18

Figure 11: Example of reading procedure starting with first status address 0X0 .....................................19

Figure 12: QFN24L (4x4 mm) package outline ........................................................................................27

Figure 13: QFN24L (4x4 mm) recommended footprint.............................................................................28