I²C bus interface

LNBH25LS

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DocID026753 Rev 3

6

I²C bus interface

Data transmission from the main microprocessor to the LNBH25LS and vice versa takes

place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up

resistors to positive supply voltage must be externally connected).

6.1

Data validity

As shown in Figure 7: "Data validity on the I²C bus", the data on the SDA line must be

stable during the high semi-period of the clock. The HIGH and LOW state of the data line

can only change when the clock signal on the SCL line is LOW.

6.2

Start and stop condition

As shown in Figure 8: "Timing diagram of I²C bus", a start condition is a HIGH to LOW

transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH

transition of the SDA line while SCL is HIGH. A stop condition must be sent before each

start condition.

6.3

Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by

an acknowledge bit. The MSB is transferred first.

6.4

Acknowledge

The master (microprocessor) puts a resistive HIGH level on the SDA line during the

acknowledge clock pulse, see Figure 9: "Acknowledge on the I²C bus". The peripheral

(LNBH25LS), which acknowledges, must pull down (LOW) the SDA line during the

acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The

peripheral, which has been addressed, has to generate acknowledge after the reception of

time. In this case the master transmitter can generate the stop information in order to abort

undervoltage lockout threshold (4.7 V typ.).

6.5

Transmission without acknowledge

Avoiding to detect acknowledges of the LNBH25LS, the microprocessor can use a simpler

transmission: it simply waits for one clock without checking the slave acknowledging, and

sends the new data. This approach is of course less protected from misworking and

decreases noise immunity.