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ST7MC1K2 数据表(PDF) 198 Page - STMicroelectronics |
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ST7MC1K2 数据表(HTML) 198 Page - STMicroelectronics |
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198 / 371 page  Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 198/371 When enabled by the SDM bit in the MCRB register, demagnetization can also be simulated by comparing the MTIM timer with the MDREG register. This kind of demagnetization is called simulated demagnetization DS. If the HDM and SDM bits are both set, the first event that occurs, triggers a demagnetization event. For this to work correctly, a DS event must not precede a DH event because the latter could be detected as a Z event. Simulated demagnetization can also be always used if the HDM bit is reset and the SDM bit is set. This mode works as a programmable masking time between the CH and Z events. To drive the motor securely, the masking time must be always greater than the real demagnetization time in order to avoid a spurious Z event. When an event occurs, (either DH or DS) the DI bit in the MISR register is set and an interrupt request is generated if the DIM bit of register MIMR is set. Caution: 1: Due to the alternate automatic capture and compare of the MTIM timer with MDREG register by DH and DS events, the MDREG register should be manipulated with special care. Caution: 2: Due to the event generation protection in the MZREG, MCOMP and MDREG registers for Soft Event generation (see Built-in checks and controls for simulated events on page 221), the value written in the MDREG register in soft demagnetization mode (SDM = 1) is checked by hardware after the C event. If this value is less than or equal to the MTIM counter value at this moment, the Software demagnetization event is generated immediately and the MTIM current value overwrites the value in the MDREG register to be able to re-use the right demagnetization time for another simulated event generation. Figure 82. D event generation mechanism 1. Preload bit, new value taken into account at the next C event (in normal mode) or when a value is written in the MPHST register when in direct access mode. For more details refer to the description of the DAC bit in Control register A (MCRA) on page 265. The use of a preload register allows all the registers to be updated at the same time 2. Register updated on R event MTIM [8-bit up counter] (2) DS MDREG [Dn] (2) Compare 8 DH DS HDM bit D= DH and HDM bit + DS and SDM bit DH SDM bit F(x) D SDM(1) bit HDMn bit (1) or 1 2 CPBn bit (1) C DS,H Sample To Z event detection To interrupt generator MCRB register MCRB register SPLG bit MCRC register SR bit MCRA register DH MDFR register DEF[3:0] DWF[3:0] MDFR register DWF[3:0] Obsolete Product(s) - Obsolete Product(s) |
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