ST7MC1K2 datasheet(200/371 Pages) STMICROELECTRONICS

200 / 371 page

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Z event generation (BEMF zero crossing)

When both C and D events have occurred, the PWM may be switched to another group of

outputs (depending on the OS[2:0] bits in the MCRB register) and the real BEMF zero

crossing sampling can start (see Figure 88). After Z event, the PWM can also be switched to

another group of outputs before the next C event.

A BEMF voltage is present on the non-powered terminal but referred to the common star

connection of the motor whose voltage is equal to VDD/2.

When a winding is free-wheeling (during PWM off-time) its terminal voltage changes to the

other power rail voltage, this means if the PWM is applied on the high side driver, free-

wheeling is done through the low side diode and the terminal is 0V.

This is used to force the common star connection to 0V in order to read the BEMF referred

to the ground terminal.

Consequently, BEMF reading (that is, comparison with a voltage close to 0V) can only be

done when the PWM is applied on the high side drivers. When the BEMF signal crosses the

threshold voltage close to zero, it is called a hardware zero-crossing event ZH. A filter can be

implemented on the ZH event detection (see Figure 84).

The Z event filter register (MZFR) is used to select the number of consecutive Z events

needed to generate the ZH event. Alternatively, the PZ bit can be used to enable protection

as described in Figure 84 on page 202

For this reason the MTC outputs can be split in two groups called LOW and HIGH and the

BEMF reading is made only when PWM is applied on one of these two groups. The REO bit

in the MPOL register is used to select the group to be used for BEMF sensing (high side

group). It has to be configured whatever the sampling mode.

When enabled by the HZ bit in MCRC register, the current value of the MTIM timer is

captured in register MZREG when this event occurs in order to be able to compute the real

delay in the delay manager part for hardware commutation but also to be able to simulate

zero-crossing events for other steps.

When enabled by the SZ bit set in the MCRC register, a zero-crossing event can also be

simulated by comparing the MTIM timer value with the MZREG register. This kind of zero-

crossing event is called simulated zero-crossing ZS.

If both HZ and SZ bits are set in MCRC register, the first event that occurs, triggers a zero-

crossing event.

Depending on the edge and level selection (ZVD and CPB) bits and when PWM is applied

on the correct group, a BEMF zero crossing detection (either ZH or ZS) sets the ZI bit in the

MISR register and generates an interrupt if the ZIM bit is set in the MIMR register.

Caution:

1: Due to the alternate automatic capture and compare of the MTIM timer with MZREG

Caution:

2: Due to the event generation protection in the MZREG, MCOMP and MDREG registers for

soft event generation, the value written in the MZREG register in simulated zero-crossing

mode (SZ = 1) is checked by hardware after the D (either DH or DS) event. If this value is

less than or equal to the MTIM counter value at this moment, the simulated zero-crossing

event is generated immediately and the MTIM current value overwrites the value in the

MZREG register. See Built-in checks and controls for simulated events on page 221.

The Z event also triggers some timer/multiplier operations, for more details see

Section 10.6.7: Delay manager.

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