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ST7MC1K2 数据表(PDF) 203 Page - STMicroelectronics

部件名 ST7MC1K2
功能描述  Clock, reset and supply management
PDF  371 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7MC1K2 数据表(HTML) 203 Page - STMicroelectronics

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On-chip peripherals
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There is no minimum off time required for current control PWM in sensor mode so the
minimum off time is set automatically to 0µs as soon as the SR bit is set in the MCRA
register and a true 100% duty cycle can be set in the PWM compare U register for the PWM
generation in voltage mode.
In sensor mode, the ZEF[3:0] bits in the MZFR register are active and can be used to define
the number of consecutive Z samples needed to generate the active event.
Procedure for reading sensor inputs in direct access mode
In direct access mode, the sensors can be read either when the clock is enabled or disabled
(depending on the CKE bit in the MCRA register). To read the sensor data the following
steps have to be performed:
1.
Select direct access mode (DAC bit in MCRA register)
2.
Select the appropriate MCIx input pin by means of the IS[1:0] bits in the MPHST
register
3.
Read the comparator output (HST bit in the MREF register)
Sampling block
For a full digital solution, the phase comparator output sampling frequency is the frequency
of the PWM signal applied to the switches and the sampling for the Z event detection in
sensorless mode is done at the end of the off time of this PWM signal to avoid to have to re-
create a virtual ground because when the PWM signal is off, the star point is at ground due
to the free-wheeling diode. That’s why, the sampling for Z event detection is done by default
during the OFF-state of the PWM signal and therefore at the PWM frequency.
In current mode, this PWM signal is generated by a combination of the output of the
measurement window generator (SA[3:0] bits), the output of the current comparator and a
minimum OFF time set by the OT[3:0] bits for system stabilization.
In voltage mode, this PWM signal is generated by the 12-bit PWM generator signal in the
compare U register with still a minimum OFF time required if the sampling is done at the end
of the OFF time of the PWM signal for system stabilization. The PWM signal is put OFF as
soon as the current feedback reaches the current input limitation. This can add an OFF time
to the one programmed with the 12-bit Timer.
For D event detection in sensorless mode, no specific PWM configuration is needed and the
sampling frequency (fSCF, see Table 166) is completely independent from the PWM signal.
In sensor mode, the D event detection is not needed as the MCIA, MCIB and MCIC pins are
the digital signals coming from the hall sensors so no specific PWM configuration is needed
and the sampling for the Z detection event is done at fSCF, completely independent from the
PWM signal.
In sensorless mode, if a virtual ground is created by the addition of an external circuit,
sampling for the Z event detection can be completely independent from the PWM signal
applied to the switches. Setting the SPLG bit in the MCRC register allows a sampling
frequency of fSCF for Z event detection independent from the PWM signal after getting the D
(end of demagnetization) event. This means that the sampling order is given whatever the
PWM signal (during the ON time or the OFF time). As soon as the SPLG bit is set in the
MCRC register, the minimum OFF time needed for the PWM signal in current mode is set to
0µs and a true 100% duty cycle can be set in the 12-bit PWM generator compare register in
voltage mode.
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