ST7MC1K2 datasheet(210/371 Pages) STMICROELECTRONICS

210 / 371 page

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Encoder mode (IS[1:0] = 11)

Figure 91 shows the signals delivered by a standard digital incremental encoder and

associated information:

●

Two 90° phased square signals with variable frequency proportional to the speed; they

must be connected to MCIA and MCIB input pins,

●

Clock derived from incoming signal edges,

●

Direction information determined by the relative phase shift of input signals (+/-90°).

The incremental encoder interface block aims at extracting these signals. As input logic is

both rising and falling edge sensitive (independently from TES[1:0] bits setting), resulting

clock frequency is four times the one of the input signals, thus increasing resolution for

measurements.

It may be noticed that direction bit (EDIR bit in MCRC register) is read only and that it does

not affect counting direction of clocked timer (see Section 10.6.7: Delay manager). As a

result, one cannot extract position information from encoder inputs during speed reversal.

Figure 90.

Tacho capture events configured by the TES[1:0] bits

Figure 91.

Incremental encoder output signals and derived information

Note:

If only one encoder output is available, it may be input either on MCIA or MCIB and an

encoder clock signal is still generated (in this case the frequency is 50% less than with two

inputs.

The state of EDIR bit depends on signals present on MCIA and MCIB pins, the result is

given by sampling the falling edges of MCIA with MCIB.

MCIA

MCIB

Encoder inputs

Direction EDIR bit

Sampling of MCIA to determine direction

Encoder clock

Tacho input

Tacho capture

TES[1:0] = 11

TES[1:0] = 01

TES[1:0] = 10

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