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ST7MC1K2 数据表(PDF) 213 Page - STMicroelectronics |
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ST7MC1K2 数据表(HTML) 213 Page - STMicroelectronics |
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213 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto On-chip peripherals 213/371 10.6.7 Delay manager This part of the MTC contains all the time-related functions. Its architecture is based on an 8-bit shift left/shift right timer shown in Figure 92. Figure 92. Overview of MTIM timer in switched and autoswitched mode 1. Register updated on R event. 2. Preload bits, new value taken into account at the next C event (in normal mode) or when a value is written in the MPHST register when in direct access mode. For more details refer to the description of the DAC bit in Control register A (MCRA) on page 265. The use of a preload register allows all the registers to be updated at the same time. The MTIM timer includes: ● An auto-updated prescaler ● A capture/compare register for simulated demagnetization simulation (MDREG) ● Two cascaded capture and one compare registers (MZREG and MZPRV) for storing the times between two consecutive BEMF zero crossings (ZH events) and for zero-crossing event simulation (ZS) ● An 8x8 bit multiplier for auto computing the next commutation time ● 1 compare register for phase commutation generation (MCOMP) The MTIM timer module can work in two main modes when driving synchronous motors in six-step mode. 8-bit up counter MTIM (1) MZREG [Zn] (1) DS MDREG [Dn] (1) Compare ZH DH ck CH,S DS,H ZH,S 8 Tratio SDM bit(2) Z clr 1 0 C SWA bit To interrupt generator To interrupt generator To interrupt generator MCRA register MCRB register Compare ZS SZ bit MCRC register ZH/ZS MZPRV [Zn-1] (1) Filter/D MZFR register ZWF[3:0] Filter/C MDFR register DWF[3:0] CH/CS Compare MCOMP [Cn+1] (1) SC bit MCRC register Obsolete Product(s) - Obsolete Product(s) |
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