ST7MC1K2 datasheet(217/371 Pages) STMICROELECTRONICS

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Autoswitched mode

In this mode, using the hardware commutation event CH (SC bit reset in MCRC register), the

MCOMP register content is automatically computed in real time as described below and in

Figure 94.

The C (either CS or CH) event has no effect on the contents of the MTIM timer.

When a ZH event occurs the MTIM timer value is captured in the MZREG register, the

previous captured value is shifted into the MZPRV register and the MTIM timer is reset. See

Figure 74.

When a ZS event occurs, the value written in the MZREG register is shifted into the MZPRV

One of these two registers, (when the SC bit = 0 in the MCRC register and depending on the

DCB bit in the MCRA register), is multiplied with the contents of the MWGHT register and

divided by 256. The result is loaded in the MCOMP compare register, which automatically

triggers the next hardware commutation (CH event).

Note:

The result of the 8*8 bit multiplication, once written in the MCOMP register is compared with

the current MTIM value to check that the MCOMP value is not already less than the MTIM

value due to the multiplication time. If MCOMP <= MTIM, a CH event is generated

immediately and the MCOMP value is overwritten by the MTIM value.

After each shift operation the multiply is recomputed for greater precision.

Using either the MZREG or MZPRV register depends on the motor symmetry and type.

The MWGHT register gives directly the phase shift between the motor driven voltage and

the BEMF. This parameter generally depends on the motor and on the speed.

Setting the SC bit in the MCRC register enables the simulated commutation event (CS)

generation. This means that a write access is possible to the MCOMP register and the

MTIM value is compared directly with the value written by software in the MCOMP register

to generate the CS event. The comparison is enabled as soon as a write access is done to

the MCOMP register. This means that if the SC bit is set and no write access is done to the

MCOMP register, the C event never occurs because no comparison is made between

MCOMP and MTIM. Therefore, it is recommended in autoswitched mode, when using

software commutation feature (SC bit is set) and for a normal event sequence, the

corresponding value to be put in MCOMP has to be written during the Z interrupt routine

(because MTIM has just been reset), so that there is no spurious comparison. If the SC bit is

set during a Z event interrupt, then, the result of the 8*8 bits hardware multiplication can be

overwritten by software in the MCOMP register. When simulated commutation mode is

enabled, the event sequence is no longer respected, meaning that the peripheral accepts

consecutive commutation events and does not necessarily wait for a D event after a Cs

event. In this case the MCOMP register can be written immediately after the previous C

event, in the C interrupt service routine for example.

Table 97.

Multiplier result

DCB bit

Commutation delay

MCOMP = MWGHT x MZPRV/256

MCOMP = MWGHT x MZREG/256

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