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ST7MC1K2 数据表(PDF) 215 Page - STMicroelectronics

部件名 ST7MC1K2
功能描述  Clock, reset and supply management
PDF  371 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ST7MC1K2 数据表(HTML) 215 Page - STMicroelectronics

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Obsolete
Product(s)
- Obsolete
Product(s)
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
On-chip peripherals
215/371
prescaler contents can be incremented/decremented at the next commutation event by setting the RMI
(decrement) or RPI (increment) bits in the MISR register. When this method is used, at the next
commutation event the prescaler value is updated but also all the MTIM timer-related registers are shifted
in the appropriate direction to keep their value. After it has been taken into account, (at commutation) the
RPI or RMI bit is reset by hardware. See Table 96.
Only one update per step is allowed, so if both RPI and RMI bits are set simultaneously by software,
there is no effect on the MISR register: the write access to these two bits together is not taken into
account and the previous state is upheld. This means that if either RPI or RMI bits were set before the
write access of both bits at the same time, this bit (RPI or RMI) is kept at 1. If neither bit was set before
the simultaneous write access, neither of them are set after the write access.
In switched mode, BEMF and demagnetization detection are already possible in order to pass in
autoswitched mode as soon as possible but Z and D events do not affect the timer contents.
In this mode, if an MTIM overflow occurs, it restarts counting from 0x00h and the OI overflow flag in the
MCRC register is set if the TES[1:0] bits = 00.
Caution:
In this mode, MCOMP must never be written to 0.
Table 96.
Step update
Mode
TES[1:0]
CKE
bit
SWA
bit
Clock
state
Read
Ratio increment
(slow down)
Ratio decrement
(speed up)
xxx
0
x
Disabled
Write the ST[3:0] value directly in the MPRSR register
Switched
00
1
0
Enabled
Set RPI bit in the MISR
register until next
commutation
Set RMI bit in the MISR
register until next
commutation
Autoswitched
00
1
1
Enabled
Automatically updated according to MZREG value
Speed measure 01 10 11
1
x
Enabled
Obsolete
Product(s)
- Obsolete
Product(s)



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