ST7MC1K2 datasheet(218/371 Pages) STMICROELECTRONICS

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Figure 94.

CH processor block

Note:

An overflow of the MTIM timer generates an RPI interrupt if the RIM bit is set.

When simulated commutation mode is enabled, the D and Z events are not ignored by the

peripheral; this means that if a Z event happens, the MTIM 8-bit internal counter is reset.

To generate consecutive simulated commutations (CS), the successive value has to be

written in the MCOMP register only after a C event generation. Otherwise, the C event never

occurs.

When simulated commutation mode is enabled, the built-in check is active, so if the value

written in the MCOMP register is less than or equal to MTIM, the C event is generated and

the data in the MCOMP register are overwritten by the MTIM value.

Auto-updated step ratio register

●

In switched mode: the MTIM timer is driven by software only and any prescaler change

has to be done by software (see Switched mode on page 214 for more details).

●

In autoswitched mode: an auto-updated prescaler always configures the MTIM timer for

best accuracy. Figure 93 illustrates the process of updating the step ratio bits:

–

When the MTIM timer value reaches 100h, the prescaler is automatically

incremented in order to slow down the MTIM timer and avoid an overflow. To keep

consistent values, the MTIM register and all the relevant registers are shifted right

(divided by two). The RPI bit in the MISR register is set and an interrupt is

generated (if RIM is set). The timer restarts counting from its median value 0 x 80h

and if the TES[1:0] bits = 00, the OI bit in the MCRC register is set.

–

When a Z-event occurs, if the MTIM timer value is below 55h, the prescaler is

automatically decremented in order to speed up the MTIM timer and keep

precision better than 1.2%. The MTIM register and all the relevant registers are

MWGHT [an+1]

MZREG [Zn]

(1)

A x B/256

MZPRV [Zn-1]

(1)

DCB bit

SWA bit = 1 and

MCOMP [Cn+1]

(1)

ZH/ZS

n-1

MCRA register

SC bit = 0

MCRC register

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