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ST7MC1K2 数据表(PDF) 241 Page - STMicroelectronics |
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ST7MC1K2 数据表(HTML) 241 Page - STMicroelectronics |
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241 / 371 page  Obsolete Product(s) - Obsolete Product(s) ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto On-chip peripherals 241/371 Figure 109. Channel manager block diagram 1. Preload register, changes taken into account at next C event. CFF[2:0] bits OO bits(1) C OE[5:0] bits 6 6 OS[2:0] bits(1) Phasen register1) SR bit 3 PWM generator Sampling frequency DAC bit Channel [5:0] Current comparator output V I PWM generator SQ R V0C1 bit V I Filter OP[5:0] bits MOE bit x6 x6 6 1 MPHST register MPOL register MCRB register MPAR register MCRA register MCRA register MCFR register Channel [5:0] Dead time 8 MDTG register 2 6 High frequency chopper HFE[1:0] bits HFRQ[2:0] bits MREF register 5 CLI bit CLIM bit OCV bit 1 1 1 OFF time ‘1’ MCRA register Sensorless sensor Sampling clock Reg C DS,H Z Events Commutation BEMF zero-crossing End of demagnetization E Emergency stop Notes Updated/shifted on R Ratio updated (+1 or -1) Multiplier overflow R+/- O Current mode Voltage mode I V Regn Updated with regn+1 1 2 Branch taken after C on C event Branch taken after D event Regn MCRA register Dead time Dead time Obsolete Product(s) - Obsolete Product(s) |
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