ST7MC1K2 datasheet(242/371 Pages) STMICROELECTRONICS

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MPHST phase state register

A preload register enables software to asynchronously update the channel configuration for

the next step (during the previous commutation interrupt routine for example): the OO[5:0]

bits in the MPHST register are copied to the phase register on a C event.

Direct access to the phase register is also possible when the DAC bit in the MCRA register

is set.

Note:

In direct access mode (DAC bit is set in MCRA register):

A C event is generated as soon as there is a write access to OO[5:0] bits in MPHST

The PWM application is selected by the OS0 bit in the MCRB register.

Regardless of the value of the CKE bit in the MCRA register, the MTIM Clock is

disabled and D and Z events are not detected.

The polarity register is used to match the polarity of the power drivers keeping the same

control logic and software. If one of the OPx bits in the MPOL register is set, this means the

switch x is ON when MCOx is VDD.

Each output status depends also on the momentary state of the PWM, its group (low or

high), and the peripheral state.

PWM features

The outputs can be split in two PWM groups in order to differentiate the high side and the

low side switches. This output property can be programmed using the OE[5:0] bits in the

MPAR register.

Table 107.

Output state

OP[5:0] bit

OO[5:0] bit

MCO[5:0] pin

1 (OFF)

0-(PWM allowed)

0 (OFF)

1-(PWM allowed)

Table 108.

DAC and MOE bit meaning

MOE bit

DAC bit

Effect on output

Reset state(1)

The reset state of the outputs can be either high impedance, low or high state depending on the

corresponding option bit.

Standard running mode

MPHST register value (depending on MPOL, MPAR register values

and PWM setting). See Table 155.

Table 109.

Meaning of the OE[5:0] bits

OE[5:0]

Channel group

High channel

Low channel

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