STM32F401CD datasheet(92/135 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F401xD STM32F401xE

92/135

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements for FT I/Os is shown in Figure 30.

VHYS

FT and NRST I/O input

hysteresis

1.7 V≤ VDD≤ 3.6 V

10%

VDD(3)

-V

BOOT0 I/O input hysteresis

1.75 V≤ VDD ≤ 3.6 V,

-40 °C≤ TA ≤ 105 °C

-100

1.7 V≤ VDD ≤ 3.6 V,

0 °C≤ TA ≤ 105 °C

Ilkg

I/O input leakage current (4)

VSS ≤ VIN ≤ VDD

±1

µA

I/O FT input leakage current (5)

VIN = 5 V

RPU

Weak pull-up

equivalent

resistor(6)

All pins

except for

PA10

(OTG_FS_ID

)

VIN = VSS

PA10

(OTG_FS_ID

)

710

RPD

Weak pull-down

equivalent

resistor(7)

All pins

except for

PA10

(OTG_FS_ID

)

VIN = VDD

PA10

(OTG_FS_ID

)

710

CIO(8) I/O pin capacitance

1. Guaranteed by design, not tested in production.

2. Guaranteed by test in production.

3. With a minimum of 200 mV.

4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 53: I/O

current injection susceptibility

5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be

higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 53: I/O current injection

susceptibility

6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the

series resistance is minimum (~10% order).

7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the

series resistance is minimum (~10% order).

Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization, not tested in production.

Table 54. I/O static characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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