STM32F769AI datasheet(44/255 Pages) STMICROELECTRONICS

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Functional overview

STM32F765xx STM32F767xx STM32F768Ax STM32F769xx

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DocID029041 Rev 4

SAI1 and SAI2 can be served by the DMA controller

2.28

SPDIFRX Receiver Interface (SPDIFRX)

The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958

and IEC-61937. These standards support simple stereo streams up to high sample rate,

and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up

to 5.1).

The main features of the SPDIFRX are the following:

•

Up to 4 inputs available

•

Automatic symbol rate detection

•

Maximum symbol rate: 12.288 MHz

•

Stereo stream from 32 to 192 kHz supported

•

Supports Audio IEC-60958 and IEC-61937, consumer applications

•

Parity bit management

•

Communication using DMA for audio samples

•

Communication using DMA for control and user channel information

•

Interrupt capabilities

The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and

decode the incoming data stream. The user can select the wanted SPDIF input, and when a

valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the

manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the

CPU decoded data, and associated status flags.

The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF

sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.

2.29

Audio PLL (PLLI2S)

The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows

to achieve error-free I2S sampling clock accuracy without compromising on the CPU

performance, while using USB peripherals.

The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change

without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.

The audio PLL can be programmed with very low error to obtain sampling rates ranging

from 8 KHz to 192 KHz.

In addition to the audio PLL, a master clock input pin can be used to synchronize the

I2S/SAI flow with an external PLL (or Codec output).

2.30

Audio and LCD PLL (PLLSAI)

An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the

PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or

11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.

The PLLSAI is also used to generate the LCD-TFT clock.

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