LP3906 datasheet(32/38 Pages) NSC

32 / 38 page

Application Notes

SYSTEM CLOCK INPUT (SYNC) PIN

Pin 23 of the chip allows for a system clock input in order to

synchronize the buck converters in PWM mode. This is

useful if the user wishes to force the bucks to work synchro-

nously with the system. Otherwise, the user should tie the

pin to GND and the bucks will operate on an internal 2 MHz

clock.

The signal applied to the SYNC pin must be 13 MHz as per

application processor specifications, but we can be con-

tacted to modify that specification if so desired. Upon input-

ting the 13 MHz clock signal, the bucks will scale it down and

continue to run at 2 MHz based off the 13 MHz clock.

ANALOG POWER SIGNAL ROUTING

All power inputs should be tied to the main VDD source (i.e.

battery), unless the user wishes to power it from another

source. (i.e. external LDO output).

The analog VDD inputs power the internal bias and error

amplifiers, so they should be tied to the main VDD. The

analog VDD inputs must have an input voltage between 2.7

and 5.5 V, as specified on pg. 6 of the datasheet.

The other V

INs(VINLDO1, VINLDO2, VIN1, VIN2) can actually

have inputs lower than 2.7V, as long as it’s higher than the

programmed output (+0.3V, to be safe).

The analog and digital grounds should be tied together

outside of the chip to reduce noise coupling.

COMPONENT SELECTION

Inductors for SW1 and SW2

There are two main considerations when choosing an induc-

tor; the inductor should not saturate and the inductor current

ripple is small enough to achieve the desired output voltage

ripple. Care should be taken when reviewing the different

saturation current ratings that are specified by different

manufacturers. Saturation current ratings are typically speci-

fied at 25oC, so ratings at maximum ambient temperature of

the application should be requested from the manufacturer.

There are two methods to choose the inductor saturation

current rating:

Method 1:

The saturation current is greater than the sum of the maxi-

mum load current and the worst case average to peak

inductor current. This can be written as follows:

RIPPLE:

Average to peak inductor current

OUTMAX: Maximum load current

IN:

Maximum input voltage to the buck

Min inductor value including worse case toler-

ances (30% drop can be considered for method 1)

Minimum switching frequency (1.6 MHz)

OUT:

Buck Output voltage

Method 2:

A more conservative and recommended approach is to

choose an inductor that has saturation current rating greater

than the maximum current limit of 2375 mA.

Given a peak-to-peak current ripple (I

PP) the inductor needs

to be at least

Inductor Value Unit Description

Notes

SW1,2

2.2

µH

SW1,2 inductor D.C.R. 70 m

Ω

External Capacitors

The regulators on the LP3906 require external capacitors for

regulator stability. These are specifically designed for por-

table applications requiring minimum board space and small-

est components. These capacitors must be correctly se-

lected for good performance.

LDO CAPACITOR SELECTION

Input Capacitor

An input capacitor is required for stability. It is recommended

that a 1.0 µF capacitor be connected between the LDO input

pin and ground (this capacitance value may be increased

without limit).

This capacitor must be located a distance of not more than 1

cm from the input pin and returned to a clean analog ground.

Any good quality ceramic, tantalum, or film capacitor may be

used at the input.

Important: Tantalum capacitors can suffer catastrophic fail-

ures due to surge currents when connected to a low imped-

ance source of power (like a battery or a very large capaci-

tor). If a tantalum capacitor is used at the input, it must be

guaranteed by the manufacturer to have a surge current

rating sufficient for the application.

There are no requirements for the ESR (Equivalent Series

Resistance) on the input capacitor, but tolerance and tem-

perature coefficient must be considered when selecting the

capacitor to ensure the capacitance will remain approxi-

mately 1.0 µF over the entire operating temperature range.

Output Capacitor

The LDOs on the LP3906 are designed specifically to work

with very small ceramic output capacitors. A 1.0 µF ceramic

capacitor (temperature types Z5U, Y5V or X7R) with ESR

between 5 m

Ω to 500 mΩ, are suitable in the application

circuit.

It is also possible to use tantalum or film capacitors at the

device output, C

OUT (or VOUT), but these are not as attrac-

tive for reasons of size and cost.

The output capacitor must meet the requirement for the

minimum value of capacitance and also have an ESR value

that is within the range 5 m

Ω to 500 mΩ for stability.

Capacitor Characteristics

The LDOs are designed to work with ceramic capacitors on

the output to take advantage of the benefits they offer. For

capacitance values in the range of 0.47 µF to 4.7 µF, ceramic

capacitors are the smallest, least expensive and have the

lowest ESR values, thus making them best for eliminating

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