LP3906 datasheet(34/38 Pages) NSC

34 / 38 page

Application Notes (Continued)

Voltage peak-to-peak ripple due to ESR can be expressed

as follows:

PP–ESR =2xIRIPPLE xRESR

Because the V

PP-C and VPP-ESR are out of phase, the rms

value can be used to get an approximate value of the peak-

to-peak ripple:

Note that the output voltage ripple is dependent on the

inductor current ripple and the equivalent series resistance

of the output capacitor (R

ESR). The RESR is frequency de-

pendent as well as temperature dependent. The R

ESR

should be calculated with the applicable switching frequency

and ambient temperature.

Capacitor

Min

Value

Unit

Description

Recommended

Type

LDO1

0.47

µF

LDO1 output

capacitor

Ceramic, 6.3V,

X5R

LDO2

0.47

µF

LDO2 output

capacitor

Ceramic, 6.3V,

X5R

SW1

10.0

µF

SW1 output

capacitor

Ceramic, 6.3V,

X5R

SW2

10.0

µF

SW2 output

capacitor

Ceramic, 6.3V,

X5R

2C Pullup Resistor

Both I

2C_SDA and I2C_SCL terminals need to have pullup

resistors connected to VINLDO12 or to the power supply of

the I

2C master. The values of the pull-up resistors (typ.

∼1.8kΩ) are determined by the capacitance of the bus. Too

large of a resistor combined with a given bus capacitance

will result in a rise time that would violate the max. rise time

specification. A too small resistor will result in a contention

with the pull-down transistor on either slave(s) or master.

Operation without I

2C Interface

Operation of the LP3906 without the I

2C interface is possible

if the system can operate with default values for the LDO and

Buck regulators. (Read below: Factory programmable op-

tions). The I

2C-less system must rely on the correct default

output values of the LDO and Buck converters.

Factory Programmable Options

The following options are EPROM programmed during final

test of the LP3906. The system designer that needs specific

options is advised to contact the local National Semiconduc-

tor sales office.

Factory programmable options

Current value

Enable delay for power on

code 010 (see

Control 1 register

section)

SW1 ramp speed

8 mV/µs

SW2 ramp speed

8 mV/µs

The I

2C Chip ID address is offered as a metal mask option.

The current value equals 0x60.

LP3906 数据表(PDF) 34 Page - National Semiconductor (TI)

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LP3906 数据表(PDF) 34 Page - National Semiconductor (TI)

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