LP3906 datasheet(17/38 Pages) NSC

17 / 38 page

SW1, SW2: Synchronous Step

Down Magnetic DC/DC Converters

(Continued)

repeated until the output reaches the desired level. Once the

output reaches the ‘high’ PFM threshold, the NMOS switch is

turned on briefly to ramp the inductor current to zero and

then both output switches are turned off and the part enters

an extremely low power mode. Quiescent supply current

during this ‘sleep’ mode is less than 30 µA, which allows the

part to achieve high efficiencies under extremely light load

conditions. When the output drops below the ‘low’ PFM

threshold, the cycle repeats to restore the output voltage to

~1.6% above the nominal PWM output voltage.

If the load current should increase during PFM mode (see

figure below) causing the output voltage to fall below the

‘low2’ PFM threshold, the part will automatically transition

into fixed-frequency PWM mode.

SW1, SW2 OPERATION

SW1 and SW2 have selectable output voltages ranging from

0.8V to 3.5V (typ.). Both SW1 and SW2 in the LP3906 are

I2C register controlled and are enabled by default through

the internal state machine of the LP3906 following a

Power-On event that moves the operating mode to the Ac-

tive state. (see Power On Sequence). The SW1 and SW2

output voltages revert to default values when the power on

sequence has been completed. The default output voltage

for each buck converter is factory programmable. (See Ap-

plication Notes).

SW1, SW2 can be enabled/disabled through the corre-

sponding control register.

The Modulation mode PWM/PFM is by default automatic

and depends on the load as described above in the func-

tional description. The modulation mode can be overridden

by setting I

2C bit to a logic 1 in the corresponding buck

control register, forcing the buck to operate in PWM mode

regardless of the load condition.

20197803

SHUTDOWN MODE

During shutdown the PFET switch, reference, control and

bias circuitry of the converters are turned off. The NFET

switch will be on in shutdown to discharge the output. When

the converter is enabled, soft start is activated. It is recom-

mended to disable the converter during the system power up

and under voltage conditions when the supply is less than

2.8V.

SOFT START

The soft-start feature allows the power converter to gradually

reach the initial steady state operating point, thus reducing

start-up stresses and surges. The two LP3906 buck convert-

ers have a soft-start circuit that limits in-rush current during

start-up. During start-up the switch current limit is increased

in steps. Soft start is activated only if EN goes from logic low

to logic high after VIN reaches 2.8V. Soft start is imple-

mented by increasing switch current limit in steps of 213 mA,

425 mA, 850 mA and 1700 mA (typ. Switch current limit). The

start-up time thereby depends on the output capacitor and

load current demanded at start-up.

LOW DROPOUT OPERATION

The LP3906 can operate at 100% duty cycle (noswitching;

PMOS switch completely on) for low drop out support of the

output voltage. In this way the output voltage will be con-

trolled down to the lowest possible input voltage. When the

device operates near 100% duty cycle, output voltage ripple

is approximately 25 mV. The minimum input voltage needed

to support the output voltage is

LP3906 数据表(PDF) 17 Page - National Semiconductor (TI)

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