SPEAR600 datasheet(13/97 Pages) STMICROELECTRONICS

13 / 97 page

SPEAr600

Architecture overview

Doc ID 16259 Rev 3

13/97

allows different subsystem data flows to be executed in parallel improving the core platform

efficiency.

High performance master agents are directly interconnected with the memory controller

reducing the memory access latency. The overall memory bandwidth assigned to each

master port can be programmed and optimized through an internal efficient weighted round-

robin arbitration mechanism.

2.1

Embedded memory units

The SPEAr600 has two embedded memory units

●

32 Kbytes of BootROM

●

8 Kbytes of SRAM

2.2

DDR/DDR2 memory controller

SPEAr600 integrates a high performance multi-channel memory controller able to support

DDR1 and DDR2 double data rate memory devices. The multi-port architecture ensures that

memory is shared efficiently among different high-bandwidth client modules.

Main features:

●

Multi channel AHB interfaces:

–

Seven independent AHB ports

–

Separate AHB memory controller programming interface

–

Support all AHB burst types

–

Lock transaction are not supported

●

Internal efficient port arbitration scheme to ensure high memory bandwidth utilization

●

Programmable register interface to control memory device parameters and protocols

●

DRAM controller supports both DDR1 and DDR2 memory devices:

–

DDR1 up to 166 MHz

–

DDR2 up to 333 MHz

●

Memory frequency with DLL enable configurable from 100 MHz to 333 MHz

●

Wide range of memory devices supported:

–

128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit, 2 Gbit

–

Two chip selects.

–

8 or 16-bit data width

2.3

Serial memory interface

SPEAr600 provides a Serial Memory Interface (SMI), acting as an AHB slave interface

(32-, 16- or 8-bit) to SPI-compatible off-chip memories.

These serial memories can be used either as data storage or for code execution.

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