SPEAR600 datasheet(17/97 Pages) STMICROELECTRONICS

17 / 97 page

SPEAr600

Architecture overview

Doc ID 16259 Rev 3

17/97

●

Native DMA with single-channel Transmit and Receive engines, providing 32/64/128-bit

data transfers

●

DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining

●

A set of CSRs to control DMA operation

●

An AHB slave acting as programming interface to access all CSRs, for both DMA and

GMAC core subsystems

●

An AHB master for data transfer to system memory

●

32-bit AHB master bus width, supporting 32-bit wide data transactions

●

Supports both big-endian and little-endian byte ordering

●

Power Management Module (PMT) with Remote Wake-up and Magic Packet frame

processing options

2.11

USB2 host controller

SPEAr600 has two fully independent USB 2.0 hosts. Each consists of 5 major blocks:

●

EHCI capable of managing high-speed transfers (HS mode, 480 Mbps)

●

OHCI that manages the full and the low speed transfers (12 and 1.5 Mbps)

●

Local 2-Kbyte FIFO

●

Local DMA

●

Integrated USB2 transceiver (PHY)

Both hosts can manage an external power switch, providing a control line to enable or

disable the power, and an input line to sense any over-current condition detected by the

external switch.

Both host controllers can perform high speed transfer simultaneously.

2.12

USB2 device controller

Main features:

●

Supports 480 Mbps high-speed mode (HS) for USB 2.0, as well as 12 Mbps full-speed

(FS) and the low-speed (LS modes) for USB 1.1

●

Supports 16 physical endpoints, which can be assigned to different interfaces and

configurations to implement logical endpoints

●

Integrated USB transceiver (PHY)

●

Local 4 Kbyte FIFO shared by all endpoints

●

DMA mode and slave-only mode are supported

●

In DMA mode, the UDC supports descriptor-based memory structures in application

memory

●

In both modes, an AHB slave is provided by UDC-AHB, acting as programming

interface to access to memory-mapped control and status registers (CSRs)

●

An AHB master for data transfer to system memory is provided, supporting 8, 16, and

32-bit wide data transactions on the AHB bus

●

A USB plug detect (UPD) which detects the connection of a cable.

SPEAR600 数据表(PDF) 17 Page - STMicroelectronics

SPEAR600 数据表(HTML) 17 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

数据表下载