SPEAR600 datasheet(14/97 Pages) STMICROELECTRONICS

14 / 97 page

Architecture overview

SPEAr600

14/97

Doc ID 16259 Rev 3

Main features:

●

Supports the following SPI-compatible Flash and EEPROM devices:

–

STMicroelectronics M25Pxxx, M45Pxxx

–

STMicroelectronics M95xxx, except M95040, M95020 and M95010

–ATMEL AT25Fxx

–YMC Y25Fxx

–

SST SST25LFxx

●

Acts always as a SPI master and supports up to 3 SPI slave memory devices (with

separate chip select signals), with up to 16 MB address space each

●

SMI clock (SMICLK) is generated by SMI (and input to all slaves) using a clock

provided by the AHB bus

●

SMI_CLK can be up to 50 MHz in fast read mode (or 20 MHz in normal mode). It can

be controlled by 7 programmable bits.

2.4

Flexible static memory controller

Root part number 1 provides Flash Nand Static Memory Controller (FSMC) which is

intended to interface an AHB bus to external NAND Flash memories.

Main purpose of FSMC is then:

●

Translate AHB protocol into the appropriate external storage device protocol

●

Meet the timing of the external devices, slowing down and counting an appropriate

number of HCLK (AHB clock) cycles to complete the transaction to the external device

Note:

The external storage device cannot be faster than one AHB cycle.

Main features of the FSMC are listed below:

●

The FSMC is an AMBA slave module connected to the AHB

●

Provides an interface between AHB system bus and Nand Flash memory devices with

8 and 16 bits wide data paths

●

FSMC performs only one access at a time and only one external device is accessed

●

Support little-endian and big-endian memory architectures

●

Handles AHB burst transfers to reduce access time to external devices

●

Supplies an independent configuration for each memory bank

●

Provides programmable timings to support a wide range of devices:

–

Programmable wait states (up to 31)

–

Programmable bus turn around cycles (up to 15)

–

Programmable output enable and write enable delays (up to 15)

●

Provides only one chip select for the first memory bank

●

Shares the address bus and the data bus with all the external peripherals, whereas

only chips selects are unique for each peripheral

●

Offers an external asynchronous wait control

●

Offers configurable size at reset for boot memory bank using external control pins.

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