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HT66F4530 数据表(PDF) 110 Page - Holtek Semiconductor Inc |
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HT66F4530 数据表(HTML) 110 Page - Holtek Semiconductor Inc |
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110 / 224 page  Rev. 1.00 110 De�e��e� �1� �01� Rev. 1.00 111 De�e��e� �1� �01� HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers Bit3 PTnOC:PTMnPTPnOutputcontrolbit CompareMatchOutputMode 0:Initiallow 1:Initialhigh PWMOutputMode/SinglePulseOutputMode 0:Activelow 1:Activehigh ThisistheoutputcontrolbitforthePTMnoutputpin.Itsoperationdependsupon whetherPTMnisbeingusedintheCompareMatchOutputModeorinthePWM OutputMode/SinglePulseOutputMode.IthasnoeffectifthePTMnisintheTimer/ CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelof thePTMnoutputpinbeforeacomparematchoccurs.InthePWMOutputModeit determinesifthePWMsignalisactivehighoractivelow.IntheSinglePulseOutput ModeitdeterminesthelogiclevelofthePTMnoutputpinwhenthePTnONbit changesfromlowtohigh. Bit2 PTnPOL:PTMnPTPnOutputpolarityControl 0:Non-invert 1:Invert ThisbitcontrolsthepolarityofthePTPnoutputpin.Whenthebitissethighthe PTMnoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.Ithasnoeffect ifthePTMnisintheTimer/CounterMode. Bit1 PTnCAPTS:PTMnCaptureTriggerSourceSelection 0:Undefined 1:FromPTCKnpin Note:WhenthePTMnisbeingusedinthecaptureinputmode,thisbitmustbesethigh. Bit0 PTnCCLR:SelectPTMnCounterclearcondition 0:PTMnComparatorPmatch 1:PTMnComparatorAmatch Thisbitisusedtoselectthemethodwhichclearsthecounter.Rememberthatthe PeriodicTMcontainstwocomparators,ComparatorAandComparatorP,eitherof whichcanbeselectedtocleartheinternalcounter.WiththePTnCCLRbitsethigh, thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA. Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfrom theComparatorPorwithacounteroverflow.Acounteroverflowclearingmethodcan onlybeimplementediftheCCRPbitsareallclearedtozero.ThePTnCCLRbitisnot usedinthePWMOutputMode,SinglePulseorCaptureInputMode. PTMnDL Register Bit 7 6 5 4 3 2 1 0 Na�e D7 D� D5 D4 D3 D� D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit7~0 D7~D0:PTMnCounterLowByteRegisterbit7~bit0 PTMn10-bitCounterbit7~bit0 PTMnDH Register Bit 7 6 5 4 3 2 1 0 Na�e — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit7~2 Unimplemented,readas"0" Bit1~0 D9~D8:PTMnCounterHighByteRegisterbit1~bit0 PTMn10-bitCounterbit9~bit8 |
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