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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HT66F4530 数据表(PDF) 100 Page - Holtek Semiconductor Inc |
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HT66F4530 数据表(HTML) 100 Page - Holtek Semiconductor Inc |
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100 / 224 page  Rev. 1.00 100 De�e��e� �1� �01� Rev. 1.00 101 De�e��e� �1� �01� HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers Timer/Counter Mode Toselectthismode,bitsSTnM1andSTnM0intheSTMnC1registershouldbesetto11 respectively.TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutput Modegeneratingthesameinterruptflags.TheexceptionisthatintheTimer/CounterModethe STMnoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompare MatchOutputModecanbeusedtounderstanditsfunction.AstheSTMnoutputpinisnotusedin thismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunction. PWM Output Mode Toselectthismode,bitsSTnM1andSTnM0intheSTMnC1registershouldbesetto10respectively andalsotheSTnIO1andSTnIO0bitsshouldbesetto10respectively.ThePWMfunctionwithin theSTMnisusefulforapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol, illuminationcontroletc.Byprovidingasignaloffixedfrequencybutofvaryingdutycycleonthe STMnoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMS values. AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgenerated waveformisextremelyflexible.InthePWMOutputMode,theSTnCCLRbithasnoeffectasthe PWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,one registerisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,while theotheroneisusedtocontrolthedutycycle.Whichregisterisusedtocontroleitherfrequency ordutycycleisdeterminedusingtheSTnDPXbitintheSTMnC1register.ThePWMwaveform frequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters. Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematch occursfromeitherComparatorAorComparatorP.TheSTnOCbitintheSTMnC1registerisused toselecttherequiredpolarityofthePWMwaveformwhilethetwoSTnIO1andSTnIO0bitsare usedtoenablethePWMoutputortoforcetheSTMnoutputpintoafixedhighorlowlevel.The STnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform. • 10-bit STMn, PWM Output Mode, Edge-aligned Mode, STnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Pe�iod 1�8 �5� 384 51� �40 7�8 89� 10�4 Duty CCRA IffSYS=4MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128, TheSTMnPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=1.9531kHz,duty=128/512=25%. IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthe PWMoutputdutyis100%. • 10-bit STMn, PWM Output Mode, Edge-aligned Mode, STnDPX=1 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Pe�iod CCRA Duty 1�8 �5� 384 51� �40 7�8 89� 10�4 ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeSTMnclock whilethePWMdutycycleisdefinedbytheCCRPregistervalue. |
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