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数据搜索系统，热门电子元器件搜索 |
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HT66F4530 数据表(PDF) 155 Page - Holtek Semiconductor Inc |
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HT66F4530 数据表(HTML) 155 Page - Holtek Semiconductor Inc |
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155 / 224 page  Rev. 1.00 154 De�e��e� �1� �01� Rev. 1.00 155 De�e��e� �1� �01� HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers UCR2 Register TheUCR2registeristhesecondofthetwoUARTcontrolregistersandservesseveralpurposes.One ofitsmainfunctionsistocontrolthebasicenable/disableoperationoftheUARTTransmitterand ReceiveraswellasenablingthevariousUARTinterruptsources.Theregisteralsoservestocontrol thebaudratespeed,receiverwake-upenableandtheaddressdetectenable.Furtherexplanationon eachofthebitsisgivenbelow: Bit 7 6 5 4 3 2 1 0 Na�e TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit7 TXEN:UARTTransmitterenabledcontrol 0:UARTtransmitterisdisabled 1:UARTtransmitterisenabled ThebitnamedTXENistheTransmitterEnableBit.Whenthisbitisequalto"0",the transmitterwillbedisabledwithanypendingdatatransmissionsbeingaborted.In additionthebufferswillbereset.InthissituationtheTXpinwillbeusedasanI/Oor otherpin-sharedfunctionalpin. IftheTXENbitisequalto"1"andtheUARTENbitisalsoequalto"1",the transmitterwillbeenabledandtheTXpinwillbecontrolledbytheUART.Clearing theTXENbitduringatransmissionwillcausethedatatransmissiontobeabortedand willresetthetransmitter.Ifthissituationoccurs,theTXpinwillbeusedasanI/Oor otherpin-sharedfunctionalpin. Bit6 RXEN:UARTReceiverenabledcontrol 0:UARTreceiverisdisabled 1:UARTreceiverisenabled ThebitnamedRXENistheReceiverEnableBit.Whenthisbitisequalto"0",the receiverwillbedisabledwithanypendingdatareceptionsbeingaborted.Inaddition thereceivebufferswillbereset.InthissituationtheRXpinwillbeusedasanI/Oor otherpin-sharedfunctionalpin.IftheRXENbitisequalto"1"andtheUARTENbit isalsoequalto"1",thereceiverwillbeenabledandtheRXpinwillbecontrolledby theUART.ClearingtheRXENbitduringareceptionwillcausethedatareceptionto beabortedandwillresetthereceiver.Ifthissituationoccurs,theRXpinwillbeused asanI/Oorotherpin-sharedfunctionalpin. Bit5 BRGH:BaudRatespeedselection 0:Lowspeedbaudrate 1:Highspeedbaudrate ThebitnamedBRGHselectsthehighorlowspeedmodeoftheBaudRateGenerator. Thisbit,togetherwiththevalueplacedinthebaudrateregisterBRG,controlsthe BaudRateoftheUART.Ifthisbitisequalto"1",thehighspeedmodeisselected.If thebitisequalto"0",thelowspeedmodeisselected. Bit4 ADDEN:Addressdetectfunctionenablecontrol 0:Addressdetectfunctionisdisabled 1:Addressdetectfunctionisenabled ThebitnamedADDENistheaddressdetectfunctionenablecontrolbit.Whenthis bitisequalto"1",theaddressdetectfunctionisenabled.Whenitoccurs,ifthe8th bit,whichcorrespondstoRX7ifBNO=0orthe9thbit,whichcorrespondstoRX8if BNO=1,hasavalueof"1",thenthereceivedwordwillbeidentifiedasanaddress, ratherthandata.Ifthecorrespondinginterruptisenabled,aninterruptrequestwillbe generatedeachtimethereceivedwordhastheaddressbitset,whichisthe8thor9th bitdependingonthevalueofBNO.Iftheaddressbitknownasthe8thor9thbitofthe receivedwordis"0"withtheaddressdetectfunctionbeingenabled,aninterruptwill notbegeneratedandthereceiveddatawillbediscarded. |
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