R5F100GD datasheet(52/202 Pages) RENESAS

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RL78/G13

1. OUTLINE

Page 52 of 196

R01DS0131EJ0330 Rev.3.30

Mar 31, 2016

[80-pin, 100-pin, 128-pin products]

Caution

This outline describes the functions at the time when Peripheral I/O redirection register (PIOR)

is set to 00H.

(1/2)

80-pin

100-pin

128-pin

Item

R5F100Mx

R5F101Mx

R5F100Px

R5F101Px

R5F100Sx

R5F101Sx

Code flash memory (KB)

96 to 512

192 to 512

Data flash memory (KB)



RAM (KB)

8 to 32

Note 1

8 to 32

Note 1

16 to 32

Note 1

Address space

1 MB

High-speed system

clock

X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)

HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),

HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),

LS (Low-speed main) mode:

1 to 8 MHz (VDD = 1.8 to 5.5 V),

LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)

Main system

clock

High-speed on-chip

oscillator

HS (High-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),

HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),

LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),

LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)

Subsystem clock

XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)

32.768 kHz

Low-speed on-chip oscillator

15 kHz (TYP.)

General-purpose register

(8-bit register

 8)  4 banks

0.03125

s (High-speed on-chip oscillator: fIH = 32 MHz operation)

0.05

s (High-speed system clock: fMX = 20 MHz operation)

Minimum instruction execution time

30.5

s (Subsystem clock: fSUB = 32.768 kHz operation)

Instruction set

 Data transfer (8/16 bits)

 Adder and subtractor/logical operation (8/16 bits)

 Multiplication (8 bits  8 bits)

 Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.

I/O port

Total

120

CMOS I/O

(N-ch O.D. I/O [EVDD withstand

voltage]: 21)

(N-ch O.D. I/O [EVDD withstand

voltage]: 24)

110

(N-ch O.D. I/O [EVDD withstand

voltage]: 25)

CMOS input

CMOS output

N-ch O.D. I/O

(withstand voltage: 6

16-bit timer

12 channels

16 channels

Watchdog timer

1 channel

Timer

Real-time clock (RTC)

1 channel

12-bit interval timer (IT)

1 channel

Timer output

12 channels

(PWM outputs: 10

Note 2)

12 channels

(PWM outputs: 10

Note 2)

16 channels

(PWM outputs: 14

Note 2)

RTC output

1 channel

 1 Hz (subsystem clock: fSUB = 32.768 kHz)

Notes 1.

The flash library uses RAM in self-programming and rewriting of the data flash memory.

The target products and start address of the RAM areas used by the flash library are shown below.

R5F100xJ, R5F101xJ (x = M, P):

Start address FAF00H

R5F100xL, R5F101xL (x = M, P, S):

Start address F7F00H

For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library

for RL78 Family (R20UT2944).

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