R5F100GD datasheet(99/202 Pages) RENESAS

99 / 202 page

RL78/G13

2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85

C)

Page 99 of 196

R01DS0131EJ0330 Rev.3.30

Mar 31, 2016

(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)

(3/3)

(TA =

40 to +85C, 1.8 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

HS (high-speed

main) Mode

LS (low-speed

main) Mode

LV (low-voltage

main) Mode

Parameter

Symbol

Conditions

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Unit

4.0 V

 EVDD0  5.5 V,

2.7 V

 Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k



110

2.7 V

 EVDD0 < 4.0 V,

2.3 V

 Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k



110

SIp setup time

(to SCKp

) Note 1

tSIK1

1.8 V

 EVDD0 < 3.3 V,

1.6 V

 Vb  2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k



110

4.0 V

 EVDD0  5.5 V,

2.7 V

 Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k



2.7 V

 EVDD0 < 4.0 V,

2.3 V

 Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k



SIp hold time

(from SCKp

) Note 1

tKSI1

1.8 V

 EVDD0 < 3.3 V,

1.6 V

 Vb  2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k



4.0 V

 EVDD0  5.5 V,

2.7 V

 Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k



2.7 V

 EVDD0 < 4.0 V,

2.3 V

 Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k



Delay time from SCKp



SOp output

Note 1

tKSO1

1.8 V

 EVDD0 < 3.3 V,

1.6 V

 Vb  2.0 V Note 2,

Cb = 30 pF, Rb = 5.5 k



Notes

1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.

2. Use it with EVDD0

 Vb.

Caution

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When

20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and

SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For

VIH and VIL, see the DC characteristics with TTL input buffer selected.

(Remarks

are listed on the next page.)

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