ADE9000 datasheet(65/73 Pages) AD

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ADE9000

Data Sheet

Rev. A | Page 64 of 72

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

0x472 PART_ID

[31:21] RESERVED

Reserved.

0x0

ADE9000_ID

This bit is set to identify an ADE9000 IC.

0x1

[19:0]

RESERVED

Reserved.

0x0

0x474 TEMP_TRIM

[31:16] TEMP_OFFSET

Offset of temperature sensor, calculated during

the manufacturing process.

0x0

R/W

[15:0]

TEMP_GAIN

Gain of temperature sensor, calculated during

the manufacturing process.

0x0

R/W

0x481 CONFIG1

EXT_REF

Set this bit if using an external voltage reference. 0x0

R/W

[14:13] RESERVED

Reserved.

0x0

IRQ0_ON_IRQ1

Set this bit to combine all the interrupts onto a

single interrupt pin, IRQ1, instead of using two

pins, IRQ0 and IRQ1. Note that the IRQ0 pin still

indicates the enabled IRQ0 events while in this

mode and the IRQ1pin indicates both IRQ1 and

IRQ0 events.

0x0

R/W

BURST_EN

Set this bit to enable burst read functionality on

the registers from Address 0x500 to Address 0x63C

or Address 0x680 to Address 0x6BC. Note that this

bit disables the CRC being appended to SPI

0x0

R/W

DIP_SWELL_IRQ_MODE

Set interrupt mode for dip/swell.

0x0

R/W

0 Receive continuous interrupts after every

DIP_CYC/SWELL_CYC cycles.

1 Receive one interrupt when entering dip/swell

mode and another interrupt when exiting

dip/swell mode.

[9:8]

PWR_SETTLE

These bits configure the time for the power and

filter-based rms measurements to settle before

starting the power, energy, and CF accumulations.

0x0

R/W

0: 64 ms.

1: 128 ms.

2: 256 ms.

3: 0 ms.

[7:6]

RESERVED

Reserved.

0x0

CF_ACC_CLR

Set this bit to clear the accumulation in the digital

to frequency converter and the CFDEN counter.

Note that this bit automatically clears itself.

0x0

RESERVED

Reserved.

0x0

[3:2]

CF4_CFG

These bits select which function to output on

the CF4 pin.

0x0

R/W

00 CF4, from digital to frequency converter.

01 CF4, from digital to frequency converter.

10 EVENT.

11 DREADY.

CF3_CFG

This bit selects which function to output on the

CF3 pin.

0x0

R/W

0 CF3, from digital to frequency converter.

1 Zero-crossing output selected by the ZX_SEL bits

in the ZX_LP_SEL register.

SWRST

Set this bit to initiate a software reset. Note that

this bit is self clearing.

0x0

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ADE9000 数据表(PDF) 65 Page - Analog Devices

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