ADE9000 datasheet(67/73 Pages) AD

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ADE9000

Data Sheet

Rev. A | Page 66 of 72

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

[6:4]

VCONSEL

3-wire and 4-wire hardware configuration

selection.

0x0

R/W

000 4-wire wye.

001 3-wire delta. VB' = VA − VC.

010 4-wire wye, nonBlondel compliant. VB' = −VA − VC.

011 4-wire delta, nonBlondel compliant. VB' = −VA.

100 3-wire delta. VA' = VA − VB; VB' = VA − VC; VC' =

VC − VB.

[3:2]

VARACC

Total and fundamental reactive power accumula-

tion mode for energy registers and CFx pulses.

0x0

R/W

00 Signed accumulation mode.

01 Absolute value accumulation mode.

10 Positive accumulation mode.

11 Negative accumulation mode.

[1:0]

WATTACC

Total and fundamental active power accumulation

mode for energy registers and CFx pulses. See

VARACC.

0x0

R/W

0x493 CONFIG3

[15:12] OC_EN

Overcurrent detection enable. OC_EN[3:0] bits

can all be set to 1 simultaneously to allow

overcurrent detection on all three phases and/or

neutral simultaneously.

0xF

R/W

Bit 12. When OC_EN[3] is set to 1, Phase A is

selected for the overcurrent detection.

Bit 13. When OC_EN[2] is set to 1, Phase B is

selected for the overcurrent detection.

Bit 14. When OC_EN[1] is set to 1, Phase C is

selected for the overcurrent detection.

Bit 15. When OC_EN[0] is set to 1, the neutral line

is selected for the overcurrent detection.

[11:5]

RESERVED

Reserved.

0x0

[4:2]

PEAKSEL

Set this bit to select which phase(s) to monitor

peak voltages and currents on. Write 1 to PEAKSEL,

Bit 0 to enable Phase A peak detection. Similarly,

PEAKSEL, Bit 1 enables Phase B peak detection, and

PEAKSEL, Bit 2 enables Phase C peak detection.

0x0

R/W

[1:0]

RESERVED

Reserved.

0x0

0x49A ZX_LP_SEL

[15:5]

RESERVED

Reserved.

0x0

[4:3]

LP_SEL

Selects line period measurement used for

VRMS½ cycle, 10 cycle rms/12 cycle rms, and

resampling.

0x3

R/W

00 APERIOD, line period measurement from Phase A

voltage.

01 BPERIOD, line period measurement from Phase B

voltage.

10 CPERIOD, line period measurement from Phase C

voltage.

11 COM_PERIOD, line period measurement on

combined signal from VA, VB, and VC.

[2:1]

ZX_SEL

Selects the zero-crossing signal, which can be

routed to the CF3/ZX output pin and used for

line cycle energy accumulation.

0x3

R/W

00 ZXVA, Phase A voltage zero-crossing signal.

01 ZXVB, Phase B voltage zero-crossing signal.

10 ZXVC, Phase C voltage zero-crossing signal.

11 ZXCOMB, zero crossing on combined signal from

VA, VB, and VC.

RESERVED

Reserved.

0x0

ADE9000 数据表(PDF) 67 Page - Analog Devices

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ADE9000 数据表(PDF) 67 Page - Analog Devices

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