ADE9000 datasheet(32/73 Pages) AD

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Data Sheet

ADE9000

Rev. A | Page 31 of 72

HPF

ZX DETECTION

LPF1

xVGAIN

PHASE

COMP

HPFDIS

ZX_SRC_SEL

VCONSEL1

VB = –VA – VC

VB = VA – VC

VB = –VA

VA = VA – VB;

VB = VA – VC;

VC = VC – VB;

xV_PCF

÷32

1VCONSEL SUPPORTS SEVERAL 3-WIRE AND 4-WIRE HARDWARE CONFIGURATIONS.

100

011

010

001

000

Figure 67. Voltage Channel Signal Chain Preceding Zero-Crossing Detection

xIGAIN

HPF

xIGAINx

PHASE

COMP

INTEGRATOR

MTEN

HPFDIS

INTEN

ICONSEL1

IB = –IA – IC

xI_PCF

ZX_SRC_SEL

ZX DETECTION

LPF1

1ICONSEL ONLY AFFECTS IB CHANNEL CALCULATION.

÷32

Figure 68. Current Channel Signal Chain Preceding Zero-Crossing Detection

POWER QUALITY MEASUREMENTS

Zero-Crossing Detection

The ADE9000 offers zero-crossing detection on the VA, VB,

VC, IA, IB, and IC input signals. The neutral current channel,

IN, does not contain a zero-crossing detection circuit. Figure 67

and Figure 68 show the current and voltage channel datapaths

preceding zero-crossing detection.

Use the ZX_SRC_SEL bit in the CONFIG0 register to select

data before the high-pass filter or after phase compensation to

configure the inputs to zero-crossing detection. ZX_SRC_SEL is

zero by default after reset.

To provide protection from noise, voltage channel zero-crossing

events (ZXVA, ZXVB, and ZXVC) do not generate if the

absolute value of the LPF1 output voltage is smaller than the

threshold, ZXTHRSH. The current channel zero-crossing

detection outputs (ZXIA, ZXIB, and ZXIC) are active for all

input signals levels.

Calculate the zero-crossing threshold, ZXTHRSH, from the

following equation:

ZXTHRSH =

(

) (

)

Attenuatio

LPF1

Scale

Full

PCF

where

V_PCF at Full Scale is ±74,532,013 decimals.

LPF1 Attenuation is 0.86 at 50 Hz, and 0.81 at 60 Hz.

x is the dynamic range below which the voltage channel zero-

crossing must be blocked.

The ADE9000 can calculate the combined zero crossings for all

three phases as (VA + VB − VC)/2 by configuring the ZX_SEL

bits in the ZX_LP_SEL register. If VCONSEL is not equal to 0,

the VB component in the combined zero-crossing circuit is set

to zero.

The zero-crossing detection circuits have two different output

rates: 8 kSPS and 1024 kSPS. The 8 kSPS zero-crossing signal

calculates the line period, updates the ZXx bits in the STATUS1

error detection, resampling, and energy accumulation functions.

The 1024 kSPS zero-crossing signal calculates the angle and

updates the zero-crossing output on the CF3/ZX pin.

CF3/ZX

The CF3/ZX pin can output zero crossings using the CF3_CFG

bit in the CONFIG1 register. To configure the source for zero

crossing, use the ZX_SEL bits in ZX_LP_SEL register. The

CF3/ZX output pin goes from low to high when a negative to

positive transition is detected and from high to low when a

positive to negative transition occurs.

Zero-Crossing Timeout

If a zero crossing is not received after (ZXTOUT + 1)/8000 sec,

the corresponding ZXTOx bit in the STATUS1 register is set

and generates an interrupt on the IRQ1 pin.

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