ADE9000 datasheet(30/73 Pages) AD

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Data Sheet

ADE9000

Rev. A | Page 29 of 72

Total and Fundamental Apparent Power

The ADE9000 offers total and fundamental apparent power

measurements on all channels. See Figure 64 for how to

calculate the total apparent power for Phase A.

AIRMSOS

APGAIN

AIRMSOS

AIRMS

AVA

AVRMS

VNOM

VNOMx_EN

LPF2

AI_PCF

215

LPF2

AI_PCF

ENERGY/

POWER/

CF ACCUMUL ATION

Figure 64. Total Apparent Power, AVA, Calculation for Phase A

The total apparent power calculations, one for each channel (AVA,

BVA, and CVA) are updated every 8 kSPS. The fundamental

apparent power is also updated every 8 kSPS and is available in

the AFVA, BFVA and CFVA registers. With full-scale inputs,

the xVA and xFVA value is 20,694,066 decimals.

The ADE9000 offers a register (VNOM) that can be set to a value

to correspond to the desired voltage rms value. If the VNOMx_EN

bits in the CONFIG0 register are set, VNOM multiplies by

xIRMS when calculating xVA.

No Load Detection, Energy Accumulation, and Power

Accumulation Features

The ADE9000 calculates the total and fundamental values of

active, reactive, and apparent energy for all the three phases. The

ADE9000 can have signed, absolute, positive, or negative only

accumulation on active and reactive energies using the WATTACC

and VARACC bits in the ACCMODE register. The default

accumulation mode is signed.

No Load Detection Feature

The ADE9000 has a no load detection for each phase and energy

to prevent energy accumulation due to noise. If the accumulated

energy over the user defined time period is below the user defined

threshold, zero energy is accumulated into the energy register.

The NOLOAD_TMR bits in the EP_CFG register determine the

no load time period and the ACT_NL_LVL, REACT_NL_LVL,

and APP_NL_LVL registers contain the user defined no load

threshold. The no load status is available in the PHNOLOAD

Energy Accumulation

The energy is accumulated into a 42-bit signed internal energy

defined number of samples or half line cycles configured by

EGY_TMR_MODE bit in the EP_CFG register. When half line

cycle accumulation is enabled, configure the zero-crossing source

using the ZX_SEL bits in the ZX_LP_SEL register. The number of

samples or half line cycles is set in the EGY_TIME register. The

maximum value of EGY_TIME is 8191d. With full-scale inputs,

the internal register overflows in 13.3 sec. For a 50 Hz signal,

EGY_TIME must be lower than 1329 decimals to prevent

overflow during half line cycle accumulation.

After EGY_TIME + 1 samples or half line cycles, the EGYRDY bit

is set in the STATUS0 register and the energy register is updated.

The data from the internal energy register is added or latched to

the user energy register depending on the EGY_LD_ACCUM

bit setting in the EP_CFG register.

The energy register is signed and is 45 bits wide, split between

two 32-bit registers, as shown in Figure 65. The user energy can

reset on a read using the RD_RST_EN bit in the EP_CFG

overflows in 106.3 sec.

Power Accumulation

The ADE9000 accumulates the total and fundamental values of

active, reactive, and apparent power for all the three phases into

respective xWATT_ACC and xFWATT_ACC, xVAR_ACC and

xFVAR_ACC, and xVA_ACC, and xFVA_ACC 32-bit signed

registers. The number of samples accumulated is set using the

PWR_TIME register. The PWRRDY bit in the STATUS0 register

is set after PWR_TIME + 1 samples accumulate at 8 kSPS. The

maximum value of the PWR_TIME register is 8191 decimals,

and the maximum power accumulation time is 1.024 sec.

The xSIGN bits in the PHSIGN register indicate the sign of

accumulated powers over the PWR_TIME interval. The PWR_

SIGN_SEL[1:0] bits allow the user to select whether the power

sign change follows the total or fundamental energies. When

sign of the accumulated power changes, the corresponding

REVx bits in the STATUS0 register are set and IRQ0 generates

an interrupt.

The ADE9000 allows the user to accumulate total active power

and VAR powers into separate positive and negative values into

the PWATT_ACC and NWATT_ACC, and PVAR_ACC and

NVAR_ ACC registers. A new accumulation from zero begins

when the power update interval set in PWR_TIMER elapses.

fDSP

INTERNAL ENERGY ACCUMULATOR

031

AWATTHR_HI

AWATT

AWATTHR_LO

Figure 65. Internal Energy Register to AWATTHR_HI and AWATTHR_LO

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