ADAV803ASTZ datasheet(32/61 Pages) AD

32 / 61 page

ADAV803

Rev. A | Page 31 of 60

AD1

AD0

AD1

AD0

SCL

SDA

START BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

FRAME 1

CHIP ADDRESS BYTE

FRAME 3

CHIP ADDRESS BYTE

FRAME 4

FRAME 2

REPEATED START

BY MASTER

ACK. BY

ADAV803

ACK. BY

ADAV803

ACK. BY

ADAV803

STOP BY

MASTER

ACK. BY

ADAV803

R/W

Figure 54. Reading from the DAC Left Volume Register in I2C

BLOCK READS AND WRITES

The ADAV803 provides the user with the ability to write to or

read from a block of registers in one continuous operation. To

use this feature, the user has to continue providing data frames

before the stop condition. For a write operation, the register

address is automatically incremented with each additional

frame and the register data is written to that register address.

For a read operation, the register address is automatically

incremented with each additional frame, and the register data is

clocked out on that frame.

Care should be exercised when using the block read or block

write modes. For most cases, block reading or writing to a

to the next register. The exceptions to this case are the indirect

memory address registers, transmitter user bit and receiver user

bit data buffers. Using a block read or write to access these

registers does not update the absolute register address, but

instead updates the buffer address to provide the next value in

the buffer.

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