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ADAV803ASTZ 数据表(PDF) 55 Page - Analog Devices |
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ADAV803ASTZ 数据表(HTML) 55 Page - Analog Devices |
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55 / 61 page ![]() ADAV803 Rev. A | Page 54 of 60 PLL Control Register 2—Address 1110101 (0x75) Table 130. PLL Control Register 2 Bit Map 7 6 5 4 3 2 1 0 FS2_1 FS2_0 SEL2 DOUB2 FS1 FS0 SEL1 DOUB1 Table 131. PLL Control Register 2 Bit Descriptions Bit Name Description FS2_[1:0] Sample rate select for PLL2. 00 = 48 kHz. 01 = Reserved. 10 = 32 kHz. 11 = 44.1 kHz. SEL2 Oversample ratio select for PLL2. 0 = 256 × fS. 1 = 384 × fS. DOUB2 Double-selected sample rate on PLL2. 0 = Disabled. 1 = Enabled. FS[1:0] Sample rate select for PLL1. 00 = 48 kHz. 01 = Reserved. 10 = 32 kHz. 11 = 44.1 kHz. SEL1 Oversample ratio select for PLL1. 0 = 256 × fS. 1 = 384 × fS. DOUB1 Double-selected sample rate on PLL1. 0 = Disabled. 1 = Enabled. |
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