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ADAV803ASTZ 数据表(PDF) 35 Page - Analog Devices

部件名 ADAV803ASTZ
功能描述  Audio Codec for Recordable DVD
PDF  61 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAV803ASTZ 数据表(HTML) 35 Page - Analog Devices

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ADAV803
Rev. A | Page 34 of 60
Record Port Control—Address 0000110 (0x06)
Table 25. Record Port Control Register Bit Map
7
6
5
4
3
2
1
0
Reserved
Reserved
CLKSRC1
CLKSRC0
WLEN1
WLEN0
SPMODE1
SPMODE0
Table 26. Record Port Control Register Bit Descriptions
Bit Name
Description
CLKSRC[1:0]
Selects the clock source for generating the OLRCLK and OBCLK.
00 = Record port is a slave.
01 = Recovered PLL clock.
10 = Internal Clock 1.
11 = Internal Clock 2.
WLEN[1:0]
Selects the serial output word length.
00 = 24 bits.
01 = 20 bits.
10 = 18 bits.
11 = 16 bits.
SPMODE[1:0]
Selects the serial format of the record port.
00 = Left-justified.
01 = I2S.
10 = Reserved.
11 = Right-justified.
Auxiliary Output Port—Address 0000111 (0x07)
Table 27. Auxiliary Output Port Register Bit Map
7
6
5
4
3
2
1
0
Reserved
Reserved
CLKSRC1
CLKSRC0
WLEN1
WLEN0
SPMODE1
SPMODE0
Table 28. Auxiliary Output Port Register Bit Descriptions
Bit Name
Description
CLKSRC[1:0]
Selects the clock source for generating the OAUXLRCLK and OAUXBCLK.
00 = Auxiliary record port is a slave.
01 = Recovered PLL clock.
10 = Internal Clock 1.
11 = Internal Clock 2.
WLEN[1:0]
Selects the serial output word length.
00 = 24 bits.
01 = 20 bits.
10 = 18 bits.
11 = 16 bits.
SPMODE[1:0]
Selects the serial format of the auxiliary record port.
00 = Left-justified.
01 = I2S.
10 = Reserved.
11 = Right-justified.



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