ADAV803ASTZ datasheet(24/61 Pages) AD

24 / 61 page

ADAV803

Rev. A | Page 23 of 60

PLL1 MCLK

PLL2 MCLK

48kHz

32kHz

44.1kHz

256

384

REG 0x75

BITS[3:2]

REG 0x75

BIT 0

REG 0x77

BIT 0

REG 0x75

BIT 1

PLL1

PLLINT1

SYSCLK1

×2

FS1

÷2

REG 0x75

BIT 5

REG 0x75

BIT 4

REG 0x77

BITS[2:1]

REG 0x75

BITS[7:6]

REG 0x74

BIT 0

PLL2

PLLINT2

SYSCLK2

SYSCLK3

48kHz

32kHz

44.1kHz

256

384

×2

FS2

FS3

÷2

256

512

Figure 38. PLL Clocking Scheme

S/PDIF TRANSMITTER AND RECEIVER

The ADAV803 contains an integrated S/PDIF transmitter and

receiver. The transmitter consists of a single output pin,

DITOUT, on which the biphase encoded data appears. The

S/PDIF transmitter source can be selected from the different

blocks making up the ADAV803. Additionally, the clock source

for the S/PDIF transmitter can be selected from the various

clock sources available in the ADAV803.

The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts

the S/PDIF input data stream. The DIRIN pin can be configured

to accept a digital input level, as defined in the Specifications

section, or an input signal with a peak-to-peak level of 200 mV

minimum, as defined by the IEC 60958-3 specification. DIR_LF

is a loop filter pin, required by the internal PLL, which is used

to recover the clock from the S/PDIF data stream.

The components shown in Figure 42 form a loop filter, which

integrates the current pulses from a charge pump and produces

a voltage that is used to tune the VCO of the clock recovery

PLL. The recovered audio data and audio clock can be routed to

the different blocks of the ADAV803, as required. Figure 39

shows a conceptual diagram of the DIRIN block.

SPDIF

*EXTERNAL CAPACITOR IS ONLY REQUIRED

FOR VARIABLE LEVEL SPDIF INPUTS.

COMPARATOR

REG 0x7A

BIT 4

DIRIN

LEVEL

SPDIF

RECEIVER

Figure 39. DIRIN Block

DIT

INPUT

DIT

PLAYBACK

AUXILIARY IN

SRC

REG 0x63

BITS[2:0]

ADC

DIR

DITOUT

CHANNEL STATUS

AND USER BITS

Figure 40. Digital Output Transmitter Block Diagram

DIR

DIRIN

AUDIO

DATA

RECOVERED

CLOCK

CHANNEL STATUS/

USER BITS

Figure 41. Digital Input Receiver Block Diagram

DIR BLOCK

DIR_LF

3.3kΩ

100nF

AVDD

6.8nF

Figure 42. DIR Loop Filter Components

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