ADAV803ASTZ datasheet(52/61 Pages) AD

52 / 61 page

ADAV803

Rev. A | Page 51 of 60

ADC Control Register 1—Address 1101110 (0x6E)

Table 116. ADC Control Register 1 Bit Map

AMC

HPF

PWRDWN

ANA_PD

MUTER

MUTEL

PLPD

PRPD

Table 117. ADC Control Register 1 Bit Descriptions

Bit Name

Description

AMC

ADC modulator clock.

0 = ADC MCLK/2 (128 × fS).

1 = ADC MCLK/4 (64 × fS).

HPF

High-pass filter enable.

0 = Normal.

1 = HPF enabled.

PWRDWN

ADC power-down.

0 = Normal.

1 = Power-down.

ANA_PD

ADC analog section power-down.

0 = Normal.

1 = Power-down.

MUTER

Mute ADC right channel.

0 = Normal.

1 = Muted.

MUTEL

Mute ADC left channel.

0 = Normal.

1 = Muted.

PLPD

PGA left power-down.

0 = Normal.

1 = Power-down.

PRPD

PGA right power-down.

0 = Normal.

1 = Power-down.

ADC Control Register 2—Address 1101111 (0x6F)

Table 118. ADC Control Register 2 Bit Map

Reserved

BUF_PD

Reserved

MCD1

MCD0

Table 119. ADC Control Register 2 Bit Descriptions

Bit Name

Description

BUF_PD

Reference buffer power-down control.

0 = Normal.

1 = Power-down.

MCD[1:0]

ADC master clock divider.

00 = Divide by 1.

01 = Divide by 2.

10 = Divide by 3.

11 = Divide by 1.

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