AD9957SLASHPCBZ datasheet(49/62 Pages) AD

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AD9957

Data Sheet

Rev. E | Page 48 of 61

SDO—Serial Data Out

Data is read from this pin for protocols that use separate lines

for transmitting and receiving data. In the case where the

AD9957 operates in a single bidirectional I/O mode, this pin

does not output data and is set to a high impedance state.

I/O_RESET—Input/Output Reset

I/O_RESET synchronizes the I/O port state machines without

affecting the addressable registers contents. An active high

input on the I/O_RESET pin causes the current communication

cycle to abort. After I/O_RESET returns low (Logic 0), another

communication cycle can begin, starting with the instruction

byte write.

I/O_UPDATE—Input/Output Update

The I/O_UPDATE initiates the transfer of written data from

the I/O port buffer to active registers. I/O_UPDATE is active

on the rising edge and its pulse width must be greater than one

SYNC_CLK period. It is either an input or output pin depending

on the programming of the Internal I/O Update Active bit.

SERIAL I/O TIMING DIAGRAMS

Figure 60 through Figure 63 provide basic examples of the tim-

ing relationships between the various control signals of the serial

I/O port. Most of the bits in the register map are not transferred

to their internal destinations until assertion of an I/O update,

which is not included in the timing diagrams that follow.

MSB/LSB TRANSFERS

The AD9957 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by Bit 0 in Control Function Register 1

(0x00). The default format is MSB first. If LSB first is active, all data,

including the instruction byte, must follow LSB-first convention.

Note that the highest number found in the bit range column for

each register is the MSB and the lowest number is the LSB for

that register (see the Register Map and Bit Descriptions section

and Table 13).

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 60. Serial Port Write Timing—Clock Stall Low

DO7

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

DON'T CARE

SDIO

SCLK

SDO

DO6 DO5 DO4 DO3 DO2 DO1

DO0

Figure 61. 3-Wire Serial Port Read Timing—Clock Stall Low

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

Figure 62. Serial Port Write Timing—Clock Stall High

SDIO

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

SCLK

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 63. 2-Wire Serial Port Read Timing—Clock Stall High

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