AD9957SLASHPCBZ datasheet(56/62 Pages) AD

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Data Sheet

AD9957

Rev. E | Page 55 of 61

The serial I/O port registers span an address range of 0 to 25

(0x00 to 0x19 in hexadecimal notation). This represents a total

of 26 registers. However, six of these registers are unused, yielding

a total of 20 available registers. The unused registers are 7, 8, 11

to 13, and 23 (0x07 to 0x08, 0x0B to 0x0D, and 0x17).

The number of bytes assigned to the registers varies. That is, the

registers are not of uniform depth; each contains the number

of bytes necessary for its particular function. Additionally, the

registers are assigned names according to their functionality.

In some cases, a register is given a mnemonic descriptor. For

example, the register at Serial Address 0x00 is named Control

Function Register 1 and is assigned the mnemonic CFR1.

The following section provides a detailed description of each bit

in the AD9957 register map. For cases in which a group of bits

serve a specific function, the entire group is considered as a

binary word and described in aggregate.

This section is organized in sequential order of the serial

addresses of the registers. Following each subheading are the

individual bit descriptions for that particular register. The

location of the bit(s) in the register are indicated by <A> or

<A:B>, where A and B are bit numbers. The notation, <A:B>,

specifies a range of bits from most significant to least significant

bit position. For example, <5:2> means bit positions 5 down to

2, inclusive, with Bit 0 identifying the LSB of the register.

Unless otherwise stated, programmed bits are not transferred to

their internal destinations until the assertion of an I/O update or

profile change.

Control Function Register 1 (CFR1)

Address 0x00, four bytes are assigned to this register.

Table 18. Bit Descriptions for CFR1 Register

Bit (s)

Mnemonic

Description

RAM Enable

0: disables RAM playback functionality (default).

1: enables RAM playback functionality.

30:29

Open

RAM Playback

Destination

Ineffective unless CFR1<31> = 1.

0: RAM playback data routed to baseband scaling multipliers (default).

1: RAM playback data routed to baseband I/Q data path.

27:26

Open

25:24

Operating Mode

00: quadrature modulation mode (default).

01: single tone mode.

1x: interpolating DAC mode.

Manual OSK

External Control

Ineffective unless CFR1<9:8> = 10b.

0: OSK pin inoperative (default).

1: OSK pin enabled for manual OSK control (see the Output Shift Keying (OSK) section).

Inverse Sinc Filter

Enable

0: inverse sinc filter bypassed (default).

1: inverse sinc filter active.

Clear CCI

This bit is automatically cleared by the serial I/O port controller. This operation requires several internal clock

cycles to complete, during which time the data supplied to the CCI input by the baseband signal chain is

ignored. The inputs are forced to all zeros to flush the CCI data path, after which the CCI accumulators are reset.

0: normal operation of the CCI filter (default).

1: initiates an asynchronous reset of the accumulators in the CCI filter.

20:17

Open

Select DDS Sine

Output

Ineffective unless CFR1<25:24> = 01b.

0: cosine output of the DDS is selected (default).

1: sine output of the DDS is selected.

15:14

Open

Autoclear Phase

Accumulator

0: normal operation of the DDS phase accumulator (default).

1: synchronously resets the DDS phase accumulator any time I/O_UPDATE is asserted or a profile

change occurs.

Open

Clear Phase

Accumulator

0: normal operation of the DDS phase accumulator (default).

1: asynchronous, static reset of the DDS phase accumulator.

Load ARR @ I/O

Update

0: normal operation of the OSK amplitude ramp rate timer (default).

1: OSK amplitude ramp rate timer reloaded any time I/O_UPDATE is asserted or a profile change occurs.

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