AD9957SLASHPCBZ datasheet(58/62 Pages) AD

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Data Sheet

AD9957

Rev. E | Page 57 of 61

Bit (s)

Mnemonic

Description

21:17

Open

Read Effective

FTW

0: a serial I/O port read operation of the FTW register reports the contents of the FTW register (default).

1: a serial I/O port read operation of the FTW register reports the actual 32-bit word appearing at the input to

the DDS phase accumulator.

15:14

I/O Update Rate

Control

Ineffective unless CFR2<23> = 1. Sets the prescale ratio of the divider that clocks the I/O update timer as

follows:

00: divide-by-1 (default).

01: divide-by-2.

10: divide-by-4.

11: divide-by-8.

PDCLK Rate

Control

Ineffective unless CFR2<31> = 0 and CFR1<25:24> = 00b.

0: PDCLK operates at the input data rate (default).

1: PDCLK operates at ½ the input data rate; useful for maintaining a consistent relationship between I/Q

words at the parallel data port and the internal clocks of the baseband signal processing chain.

Data Format

0: the data-words applied to Pin D<17:0> are expected to be coded as twos complement (default).

1: the data-words applied to Pin D<17:0> are expected to be coded as offset binary.

PDCLK Enable

0: the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal continues to operate

and provide timing to the data assembler.

1: the internal PDCLK signal appears at the PDCLK pin (default).

PDCLK Invert

0: normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default).

1: inverted PDCLK polarity.

TxEnable Invert

0: normal TxENABLE polarity; Logic 0 is standby, Logic 1 is transmit (default).

1: inverted TxENABLE polarity; Logic 0 is transmit, Logic 1 is standby.

Q-First Data

Pairing

0: an I/Q data pair is delivered as I-data first, followed by Q-data (default).

1: an I/Q data pair is delivered as Q-data first, followed by I-data.

Open

Data Assembler

Hold Last Value

Ineffective when CFR1<25:24> = 01b.

0: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces zeros on

the baseband signal path (default).

1: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces the last

value received on the baseband signal path.

Sync Timing

Validation Disable

0: enables the setup and hold validation circuit to take a measurement; the measurement result appears at

the SYNC_SMP_ERR pin; a Logic 1 at this pin indicates a potential setup/hold violation whereas a Logic 0

indicates that a setup/hold violation has not been detected; the measurement result is latched and held until

this bit is set to a Logic 1.

1: resets the setup and hold validation measurement circuit forcing the SYNC_SMP_ERR pin to a static Logic 0

condition (default); the measurement circuit is effectively disabled until this bit is restored to a Logic 0 state.

4:0

Open

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