AD9957SLASHPCBZ datasheet(20/62 Pages) AD

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Data Sheet

AD9957

Rev. E | Page 19 of 61

INTERPOLATING DAC MODE

A block diagram of the AD9957 operating in interpolating DAC

mode is shown in Figure 28; grayed items are inactive. In this

mode, the Q data path, DDS, and modulator are all disabled; only

the I data path is active.

As in quadrature modulation mode, the PDCLK pin functions

as a clock, synchronizing the input of data to the AD9957.

No modulation takes place in the interpolating DAC mode;

therefore, the spectrum of the data supplied at the parallel port

remains at baseband. However, a sample rate conversion takes

place based on the programmed interpolation rate. The inter-

polation hardware processes the signal, effectively performing

an oversample with a zero-stuffing operation. The original

input spectrum remains intact and the images that otherwise

would occur from the sample rate conversion process are

suppressed by the interpolation signal chain.

PDCLK

I/Q IN

DAC_RSET

IOUT

TxENABLE

DAC GAIN

CLOCK

SYSCLK

PLL

÷2

REF_CLK

REFCLK_OUT

XTAL_SEL

PARALLEL DATA

TIMING AND CONTROL

AD9957

cos (ωt+θ)

sin (ωt+θ)

DDS

AUX

DAC

8-BIT

POWER

DOWN

CONTROL

OSK

INTERNAL CLOCK TIMING AND CONTROL

DAC

14-BIT

FTW

RAM

SERIAL I/O

PORT

PROGRAMMING

REGISTERS

I Q

IS QS

OUTPUT

SCALE

FACTOR

Figure 28. Interpolating DAC Mode

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