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AD7653ACPZ 数据表(PDF) 8 Page - Analog Devices |
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AD7653ACPZ 数据表(HTML) 8 Page - Analog Devices |
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8 / 27 page ![]() Data Sheet AD7653 Rev. C | Page 7 of 26 ABSOLUTE MAXIMUM RATINGS Table 5. AD7653 Absolute Maximum Ratings Parameter Rating IN1, TEMP1,REF, REFBUFIN, INGND, REFGND to AGND AVDD + 0.3 V to AGND – 0.3 V Ground Voltage Differences AGND, DGND, OGND ±0.3 V Supply Voltages AVDD, DVDD, OVDD –0.3 V to +7 V AVDD to DVDD, AVDD to OVDD ±7 V DVDD to OVDD –0.3 V to +7 V Digital Inputs –0.3 V to DVDD + 0.3 V PDREF, PDBUF2 ±20 mA Internal Power Dissipation3 700 mW Internal Power Dissipation4 2.5 W Junction Temperature 150°C Storage Temperature Range –65°C to +150°C Lead Temperature Range (Soldering 10 sec) 300°C 1 See Analog Input section. 2 See Voltage Reference Input section. 3 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W 4 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. IOH 500µA 1.6mA IOL TO OUTPUT PIN 1.4V CL 60pF* *IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. 02966-0-006 Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs CL = 10 pF 0.8V 2V 2V 0.8V 0.8V 2V tDELAY tDELAY 02966-0-007 Figure 3. Voltage Reference Levels for Timing ESD CAUTION |
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