Data Sheet

AD7653

Rev. C | Page 21 of 26

MASTER SERIAL INTERFACE

Internal Clock

The AD7653 is configured to generate and provide the serial

data clock SCLK when the EXT/INT pin is held LOW. The

AD7653 also generates a SYNC signal to indicate to the host

when the serial data is valid. The serial clock SCLK and the

SYNC signal can be inverted, if desired. Depending on the

RDC/SDIN input, the data can be read after each conversion or

during the following conversion. Figure 32 and Figure 33 show

the detailed timing diagrams of these two modes.

Usually, because the AD7653 is used with a fast throughput, the

Master Read During Conversion mode is the most

recommended serial mode. In this mode, the serial clock and

data toggle at appropriate instants, minimizing potential

feedthrough between digital activity and critical conversion

decisions.

In Read After Conversion mode, it should be noted that unlike

in other modes, the BUSY signal returns LOW after the 16 data

bits are pulsed out and not at the end of the conversion phase,

which results in a longer BUSY width.

BUSY

SYNC

SCLK

SDOUT

12

3

14

15

16

D15

D14

D2

D1

D0

X

RDC/SDIN = 0

INVSCLK = INVSYNC = 0

02966-0-015

CNVST

CS, RD

EXT/INT = 0

Figure 32. Master Serial Data Timing for Reading (Read after Convert)

EXT/INT = 0

RDC/SDIN = 1

INVSCLK = INVSYNC = 0

D15

D14

D2

D1

D0

X

1

2

3

14

15

16

BUSY

SYNC

SCLK

SDOUT

02966-0-016

CNVST

CS, RD

Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)