AD7653

Data Sheet

Rev. C | Page 10 of 26

Pin No.

Mnemonic

Description

32

CS

DI

Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS

is also used to gate the external clock.

33

RESET

DI

Reset Input. When set to a logic HIGH, this pin resets the AD7653 and the current conversion, if any,

is aborted. If not used, this pin could be tied to DGND.

34

PD

DI

Power-Down Input. When set to logic HIGH, power consumption is reduced and conversions are

inhibited after the current one is completed.

35

CNVST

DI

Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and

initiates a conversion. In Impulse mode (IMPULSE HIGH, WARP LOW), if CNVST is held LOW when the

conversion is immediately started.

37

REF

AI/O

Reference Input Voltage. On-chip reference output voltage.

38

REFGND

AI

Reference Input Analog Ground.

39

INGND

AI

Analog Input Ground.

43

IN

AI

Primary Analog Input with a Range of 0 V to 2.5 V.

45

TEMP

AO

Temperature Sensor Voltage Output.

46

REFBUFIN

AI/O

Reference Input Voltage. The reference output and the reference buffer input.

47

PDREF

DI

This pin allows the choice of internal or external voltage references. When LOW, the on-chip

reference is turned on. When HIGH, the internal reference is switched off and an external reference

must be used.

48

PDBUF

DI

This pin allows the choice of buffering an internal or external reference with the internal buffer.

When LOW, the buffer is selected. When HIGH, the buffer is switched off.

1

AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power.