AD7653

Data Sheet

Rev. C | Page 8 of 26

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

02966-0-002

AGND

AVDD

NC

BYTESWAP

OB/2C

WARP

IMPULSE

SER/PAR

D0

D1

D3/DIVSCLK1

D2/DIVSCLK0

AGND

CNVST

PD

RESET

CS

RD

DGND

BUSY

D15

D14

D13

D12

1

2

3

4

5

6

7

25

26

27

28

29

30

31

32

33

34

35

36

8

9

10

11

12

AD7653

TOP VIEW

(Not to Scale)

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE LFCSP PACKAGE HAS AN EXPOSED PAD. THIS EPAD CAN

BE CONNECTED AGND. THIS CONNECTION IS NOT REQUIRED

TO MEET ELECTRICAL PERFORMANCE SPECIFICATIONS.

Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48-1)

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

0

EPAD

Exposed Pad. The LFCSP package has an exposed pad. This EPAD can be connected to AGND. This

connection is not required to meet electrical performance specifications.

1, 36,

41, 42

AGND

P

Analog Power Ground Pin.

2, 44

AVDD

P

Input Analog Power Pin. Nominally 5 V.

3, 40

NC

No Connect.

4

BYTESWAP

DI

Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on

D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].

5

OB/2C

DI

Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary;

when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift

register.

6

WARP

DI

Mode Selection. When this pin is HIGH and the IMPULSE pin is LOW, this input selects the fastest

mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in

order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of

the minimum conversion rate.

7

IMPULSE

DI

Mode Selection. When IMPULSE is HIGH and WARP is LOW, this input selects a reduced power

mode. In this mode, the power dissipation is approximately proportional to the sampling rate.

8

SER/PAR

DI

Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial

interface mode is selected and some bits of the DATA bus are used as a serial port.

9, 10

D[0:1]

DO

Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high

impedance.

11, 12

D[2:3]or

DIVSCLK[0:1]

DI/O

When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.

When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert),

these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that

clocks the data output. In other serial modes, these pins are not used.