BLUENRG-2 datasheet(45/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

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3.7.2.5

Error management

A DMA transfer error can be generated by reading from or writing to a reserved address

space. When a DMA transfer error occurs during a DMA read or a write access, the faulty

channel is automatically disabled through a hardware clear of its EN bit in the

corresponding Channel configuration register (DMA_CCRx). The channel's transfer error

interrupt flag (TEIF) in the ISR register is set and an interrupt is generated if the transfer

error interrupt enable bit (TEIE) in the DMA_CCRx register is set.

3.7.2.6

Interrupts

An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for

each DMA channel. Separate interrupt enable bits are available for flexibility.

Table 42: DMA interrupt requests

Interrupt event

Event flag

Enable control bit

Half-transfer

HTIF

HTIE

Transfer complete

TCIF

TCIE

Transfer error

TEIF

TEIE

3.7.2.7

DMA request mapping

The eight requests from the peripherals (SPI, I2Cx[1,2] and UART) are multiplexed before

entering DMA with the ADC request. For each channel, the choice between the peripheral

and the ADC is done through the DMA_CONFIG register.

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