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BLUENRG-2 数据表(PDF) 21 Page - STMicroelectronics |
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BLUENRG-2 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 190 page  BlueNRG-2 Functional details DocID030675 Rev 2 21/190 Table 9: SYSTEM_CTRL – SLEEPIO_OUT register description: address offset SYSTEM_CTRL_BASE_ADDR+0x10 Bit Field name Reset RW Description 4:0 SLEEPIO_OUT 0x00 RW Writing to a bit will drive the written value on the corresponding IO when it is configured in output direction in SLEEPIO_OEN register. Reading a bit in this register returns the last written value. One bit by IO: - Bit0: IO9 - Bit1: IO10 - Bit2: IO11 31:5 RESERVED 0x00 R RESERVED Table 10: SYSTEM_CTRL - SLEEPIO_DS register description: address offset SYSTEM_CTRL_BASE_ADDR+0x14 Bit Field name Reset RW Description 4:0 SLEEPIO_DS 0x00 RW Configure the drive strength. 0: low drive strength. 1: high drive strength. One bit by IO: - Bit0: IO9 - Bit1: IO10 - Bit2: IO11 31:5 RESERVED 0x00 R RESERVED Table 11: SYSTEM_CTRL - SLEEPIO_PE register description: address offset SYSTEM_CTRL_BASE_ADDR+0x18 Bit Field name Reset RW Description 4:0 SLEEPIO_PE 0x00 RW Configure the pullability. 0: pull disabled. 1: pull enabled. One bit by IO: - Bit0: IO9 - Bit1: IO10 - Bit2: IO11 31:5 RESERVED 0x00 R RESERVED AHBUPCONV peripheral base address (AHBUPCONV_BASE_ADDR) 0x40C00000. Table 12: AHBUPCONV registers Address offset Name RW Reset Description 0x00 COMMAND RW 0x00000000 AHB up/down converter command register BLUE_CTRL peripheral base address (BLUE_CTRL_BASE_ADDR) 0x48000000. Table 13: BLUE_CTRL registers Address offset Name RW Reset Description 0x04 TIMEOUT RW 0x00000000 Timeout programming register 0x0C RADIO_CONFIG RW 0x00000000 Radio configuration register 3.5 Clocks and reset management The BlueNRG-2 embeds an RC low-speed frequency oscillator at 32 kHz and an RO high- speed frequency oscillator at 16 MHz. |
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