BLUENRG-2 datasheet(78/190 Pages) STMICROELECTRONICS

78 / 190 page

Functional details

BlueNRG-2

78/190

DocID030675 Rev 2

Table 78: UART - DR register description: address offset UART_BASE_ADDR+0x00

Bit

Field name

Reset

Description

7:0

DATA

0x0

UART data register:

Receive: read data character.

Transmit: write data character.

0x0

Frame error. This bit is set to 1 if the received character did

not have a valid stop bit. In FIFO mode, this error is

associated with the character at the top of the FIFO.

0x0

Parity error. This bit is set to 1 if the parity of the received data

character does not match the parity selected as defined by

bits 2 and 7 of the LCRH_RX register. In FIFO mode, this

error is associated with the character at the top of the FIFO.

0x0

Break error. This bit is set to 1 if a break condition was

detected, indicating that the received data input was held low

for longer than a full-word transmission time (defined as start,

data, parity and stop bits). In FIFO mode, this error is

associated with the character at the top of the FIFO. When a

break occurs, only one 0 character is loaded into the FIFO.

The next character is only enabled after the receive data input

goes to HIGH (marking state), and the next valid start bit is

received

0x0

Overrun error. This bit is set to 1 if data is received and the

receive FIFO is already full. This is cleared to 0b once there is

an empty space in the FIFO and a new character can be

written to it. The FIFO content remains valid since no further

data is written when the FIFO is full, only the content of the

shift register is overwritten.

31:12

RESERVED

0x0

RESERVED

Table 79: UART - RSR register description: address offset UART_BASE_ADDR+0x04

Bit

Field name

Reset

Description

0x0

Frame error. This bit is set to 1 if the received character did not

have a valid stop bit (a valid stop bit is 1).This bit is cleared to

0b after a write to ECR. In FIFO mode, this error is associated

with the character at the top of the FIFO.

0x0

Parity error. This bit is set to 1 if the parity of the received data

character does not match the parity selected as defined by bits

2 and 7 of the LCRH_RX register.This bit is cleared to 0b after

a write to ECR. In FIFO mode, this error is associated with the

character at the top of the FIFO.

0x0

Break error. This bit is set to 1 if a break condition was

detected, indicating that the received data input was held low

for longer than a full-word transmission time (defined as start,

data, parity and stop bits). This bit is cleared to 0b after a write

to ECR. In FIFO mode, this error is associated with the

character at the top of the FIFO. When a break occurs, only

one 0 character is loaded into the FIFO. The next character is

only enabled after the receive data input goes to HIGH

(marking state), and the next valid start bit is received.

BLUENRG-2 数据表(PDF) 78 Page - STMicroelectronics

BLUENRG-2 数据表(HTML) 78 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载