BLUENRG-2 datasheet(47/190 Pages) STMICROELECTRONICS

47 / 190 page

BlueNRG-2

Functional details

DocID030675 Rev 2

47/190

Bit

Field name

Reset

Description

TCIF0

0x0

Channel 0 transfer complete flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 0.

1: A transfer complete (TC) occurred on channel 0.

HTIF0

0x0

Channel 0 half transfer flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 0.

1: A half transfer (HT) event occurred on channel 0.

TEIF0

0x0

Channel 0 transfer error flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 0.

1: A transfer error (TE) occurred on channel 0.

GIF1

0x0

Channel 1 global interrupt flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 1.

1: A TE, HT or TC event occurred on channel 1.

TCIF1

0x0

Channel 1 transfer complete flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 1.

1: A transfer complete (TC) occurred on channel 1.

HTIF1

0x0

Channel 1 half transfer flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 1.

1: A half transfer (HT) event occurred on channel 1.

TEIF1

0x0

Channel 1 transfer error flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 1.

1: A transfer error (TE) occurred on channel 1.

GIF2

0x0

Channel 2 global interrupt flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 2.

1: A TE, HT or TC event occurred on channel 2.

TCIF2

0x0

Channel 2 transfer complete flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 2.

1: A transfer complete (TC) occurred on channel 2.

BLUENRG-2 数据表(PDF) 47 Page - STMicroelectronics

BLUENRG-2 数据表(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

BLUENRG-2 数据表(PDF) 47 Page - STMicroelectronics

BLUENRG-2 数据表(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载