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BLUENRG-2 数据表(PDF) 28 Page - STMicroelectronics |
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BLUENRG-2 数据表(HTML) 28 Page - STMicroelectronics |
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28 / 190 page  Functional details BlueNRG-2 28/190 DocID030675 Rev 2 Bit Field name Reset RW Description 3 UART 0x1 RW UART clock 4 SPI 0x1 RW SPI clock 6:5 RESERVED 0x3 R RESERVED 7 WDOG 0x1 RW Watchdog clock 8 ADC 0x1 RW ADC clock 9 I2C1 0x1 RW I2C1 clock 10 I2C2 0x1 RW I2C2 clock 11 MFT1 0x1 RW MFT1 clock 12 MFT2 0x1 RW MFT2 clock 13 RTC 0x1 RW RTC clock 15:14 RESERVED 0x3 R RESERVED 16 DMA 0x1 RW DMA AHB clock 17 RNG 0x1 RW RNG AHB clock 18 PKA 0x0 RW PKA AHB clock 19 PKA RAM 0x0 RW PKA RAM clock 31:20 RESERVED 0x0 R RESERVED Table 19: CKGEN_SOC - DMA_CONFIG register description: address offset CKGEN_SOC_BASE_ADDR+0x24 Bit Field name Reset RW Description 0 ADC_CH0 0x0 RW Select ADC on DMA channel 0 instead of peripheral 1 ADC_CH1 0x0 RW Select ADC on DMA channel 1 instead of peripheral 2 ADC_CH2 0x0 RW Select ADC on DMA channel 2 instead of peripheral 3 ADC_CH3 0x0 RW Select ADC on DMA channel 3 instead of peripheral 4 ADC_CH4 0x0 RW Select ADC on DMA channel 4 instead of peripheral 5 ADC_CH5 0x0 RW Select ADC on DMA channel 5 instead of peripheral 6 ADC_CH6 0x0 RW Select ADC on DMA channel 6 instead of peripheral 7 ADC_CH7 0x0 RW Select ADC on DMA channel 7 instead of peripheral 31:8 RESERVED 0x0 R RESERVED |
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